Texas Instruments Incorporated Deutschland, Gmbh

Texas Instruments Corporation

Markus Dietl

Siva RaghuRam Prasad Chennupati

Sotirios Tambouris

Puneet Sareen

Ketan Dewan

Dinesh Jain

Joern Naujokat

Hermann Seibold

Ralf Sonnhueter

Edmond F George

Lmar Werkmeister

A linear actuator includes a piston, a transmitter, and a receiver. The piston is configured to linearly extend and retract (such as within a cover tube). The transmitter is configured to generate a transmit electromagnetic waveform and direct the transmit electromagnetic waveform along a length of the piston. The receiver is configured to receive a return electromagnetic waveform that includes the transmit electromagnetic waveform after travelling to an extended end of the piston and returning to the receiver and determine a position of the piston based on a phase difference between the transmit electromagnetic waveform and the return electromagnetic waveform.

Time of flight absolute position measurement

A full quadrant analog interpolator used in a fractional clock generator. A quadrature clock signal with minimal jitter is provided to the full quadrant analog interpolator. The full quadrant analog interpolator uses a series of switches and current sources to develop a differential output signal based on a digital input value, thus allowing digital control of the delay developed by the full quadrant analog interpolator. The differential output of the full quadrant analog interpolator is provided to multi-stage comparator. The output of the multi-stage comparator is provided to an integer divider to provide the final output clock. A digital control section utilizes a &#x3a3;&#x394; modulator and a summer to utilize an input N.&#x3b1; control input which provides the desired fractional division amount to provide a signal to a phase accumulator. The output of the phase accumulator is the digital control or &#x3b2; value of the full quadrant analog interpolator.

Fractional clock generator

Termination impedance of a digital signal bus is adaptively selected as a function of a present or anticipated state of the bus. A variable termination resistor is arranged in series between a termination switch and a common voltage node at the termination end of each bus conductor. Information regarding the current or anticipated bus state is received from an external device such as a bus controller or may be derived by sensing activity on the bus. For example, clock frequency detection logic coupled to clock lines of the bus senses the current operational speed of the bus. A highest-value termination resistance predetermined to be consistent with reliable bus operation under conditions of the current or anticipated bus state is selected for each bus conductor. A bus conductor termination may be taken to a high impedance state by opening the associated termination switch. Decreased average bus power consumption may result.

Adaptive bus termination apparatus and methods

The invention generally relates to phase locked loops (PLL), and more specifically to ultra-low bandwidth phase locked loops. The invention may be for example embodied in an integrated circuit implementing a phase locked loop or a method for operating a phase locked loop. The invention provides a PLL with a control stage that uses only two storage cells, a counter and a digital-to-analog (DAC) converter. In comparison to prior-art PLLs using storage cells the configuration of the invention's control stage reduces the chip area required for the PLL reduced. The invention further suggests PVT compensation mechanisms for a PLL and implementing a PLL that has lower peaking in its frequency response, which results in better settling response.

Phase locked loop and method for operating the same

A phase locked loop (PLL) is provided. The PLL includes a control stage comprising N storage elements each having an output coupled to the output of the control stage. The N storage elements being coupled in a chain, and each storage element being configurable in an analog mode, where a stored signal at the storage node of the storage element is changed continuously in response to the output signal of a charge pump. Each storage element is configurable in a digital mode in which the stored value is one value out of a predetermined set of values, and the storage element can assume the analog mode if a preceding storage element and a subsequent storage element are in the digital mode and have different values of the stored signal.

Electronic device and method for phase locked loop

An integrated phase adjusting circuit () for the generation of a clock output signal (CLK) with a phase intermediate the phases of first and second input signals of equal frequency with a fixed phase shift between said first and second signals is proposed. The circuit has an interpolator unit () which determines the phase of the clock signal relative to either one of the first input signal and the second input signal, and is controlled externally by a control signal (PH) to execute a phase step if the phase of the clock signal is to be shifted. The circuit () comprises a synchronization unit () which synchronizes the phase step with the clock output signal generated by the circuit.

Phase adjusting circuit for minimized irregularities at phase steps

An integrated circuit device comprises internally on-chip an oscillator with a signal output. The device has a reference clock input, a first counter with a count input, a control input and a counter output, a second counter with a count input, a control input and an overflow indication output, and a test control logic circuit. The count input of the first counter is connected to the signal output of the oscillator. The count input of the second counter is connected to the reference clock input. The overflow indication output of the second counter is connected to an input of the test control logic circuit. The test control circuit has an output connected to the control input of the first counter to apply a stop counting control signal to the first counter after it has received an overflow indication signal from the second counter. The first counter after it has received a stop counting control signal provides a count at the counter output which is indicative of the output frequency of the oscillator. The device includes all the hardware necessary to perform an on-chip test of the oscillator, thereby obviating the need for serial testing on sophisticated and expensive test equipment.

Integrated circuit device

A circuit generating an output phase signal with an optionally variable phase shift relative to a reference phase. It includes an oscillator () outputting phase signals at n outputs, each of which differs in phase by &#x3c6;=360&#xb0;/n. These phase signals are applied selectively via multiplexers to a phase interpolator, at the output of which the signal changed in phase relative to a reference phase. The output phase signal is generated in a charging circuit in which a capacitor can be varied by signaling current sources ON/OFF with the aid of phase switches in accordance with the phasing to be produced for the output signal. To avoid jitter in the transition from one phase to another separating switches are inserted in the connection between the current sources and the charging circuit, these separating switches being controlled so that they are never open at the same time.

Circuit for generating an output phase signal with a variable phase shift relative to a reference phase

An output driver circuit includes an input stage to which an input voltage is applied, and an output stage to which an output voltage is applied, input stage and output stage being connected by at least one supply voltage terminal and/or at least one ground terminal to which at least one parasitic inductance is applied, and the input stage and output stage being configured so that when the difference amount between a potential as a function of the input voltage and a potential as a function of the supply voltage and/or ground voltage exceeds a predefined first threshold value or drops below a predefined second threshold value a flow of current is activated or deactivated respectively in the output stage via the supply voltage terminal(s) and/or the ground terminal(s) which also flows via the parasitic inductance(s). The output driver circuit in includes in addition, a circuit element connected to the input voltage capable of 'seeing' or determining whether the input voltage in a predefined interval hovers around a value corresponding to the first threshold value or second threshold value and that, if so, a control signal is generated with which changes in the flow of current in the output stage are reduced until the input voltage is outside of the predefined interval.

Output driver circuit

A phase-locked loop (PLL) has a phase detector coupled to an output of the PLL and to a reference signal and a low pass filter including a first and a second charge pump coupled to an output of the phase detector. A capacitor is coupled to an output of the first charge pump, a first bias circuit coupled to the capacitor, the first bias circuit having a differential output. A voltage controlled ring oscillator has a plurality of differential inventer stages, each having a first input coupled to a first output of the first bias circuit and a second input coupled to a second output of the first bias circuit. A second bias circuit is coupled between the capacitor and the first bias circuit, an output of the second bias circuit being coupled to an input of the first bias circuit and to an output of the second charge pump. The PLL circuit exhibits a stable damping factor with respect to frequency.

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Munich, Germany

Markus Dietl