International Business Machines Corporation

Markus Buehler

Juergen Koehl

Jeanne P Bickford

Jason D Hibbeler

Philipp Panitz

Markus Olbrich

Edward J Nowak

Brent A Anderson

Adam P Matheny

James J Curtin

Douglas S Search

Thomas Buechner

Charles Kyriakos Vakirtzis

Dhaval R Sejpal

Moussadek Belaidi

Bryan A Meyer

Lei Wang

Burkhard Steinmacher-Burow

Thomas Schwarz

Rainer Dorsch

Guenther Hutzl

Stefanie Scherzinger

Cagri Balkesen

Arni Ingimundarson

Thilo Maurer

Michael W Kaufmann

Daniel Pfefferkorn

David Rohr

David James Hathaway

John Maxwell Cohn

Diwesh Pandey

Daniel Nelson Maynard

Uwe Brandt

Sven Peyer

Andreas Arp

Sebastian Ehrenreich

Jens Noack

Philipp Salz

Thomas Kalla

Monika Strohmer

Hans-Werner Anderson

Ankit Gangwar

Arun K Mishra

Benedikt Rombach

Katherine Eve

Juergen Kuehl

Aspects of the disclosure relate to a processor core including an execution unit and a usage ratio controller. The execution unit is operable for executing a command forwarded to the execution unit. The usage ratio controller is operatively coupled with the execution unit. The usage ratio controller is operable for controlling a usage ratio of the execution unit. The usage ratio corresponds to the fraction of an observation time during which the execution unit is executing commands of an application. Other aspects of the disclosure relate to a method for detecting or analyzing a bottleneck in a processor core for a given application. The method includes controlling a usage ratio of at least one execution unit of the processor core and measuring the resulting application performance.

Partial computer processor core shutoff

A buffer is configured to store a plurality of last addresses accessed by a processor core from a memory. A minimum distance extraction circuit determines distances of a current memory address accessed by the processor core from each of the plurality of last addresses in the buffer and determines a minimum distance from the distances. A limit determination circuit compares the minimum distance to each of a plurality of ranges of distances and selects a range of the plurality of ranges within which the minimum distance falls. Each of a plurality of counters of a counter circuit is associated with a corresponding one of the plurality of ranges. A counter of the plurality of counters is to be incremented corresponding to the selected range.

Hardware apparatus to measure memory locality

A method, computer program product, and system for rerouting wires based on wire size and spacing requirements including partitioning a chip into a plurality of global routing tiles, assigning a set of wires to one or more of the plurality of global routing tiles, sorting the set of wires into one or more groups based on line spacing requirements for wires of the set of wires, each of the one or more groups includes one or more wires with a common line spacing requirement, and organizing the one or more groups in a numeric order based on the common line spacing requirement of each group.

Congestion mitigation by wire ordering

A method for implementing a hardware design that includes using a computer for receiving structured data that includes a representation of a basic hardware structure and a complex hardware structure that includes the basic hardware structure, parsing the structured data and generating, based on a result of the parsing, commands of a hardware design environment.

Parsing data representative of a hardware design into commands of a hardware design environment

Calculating a timing delay in a repeater network in an electronic circuit. The repeater network comprises a plurality of driving cells. At least one loop comprising one or more pins and one or more driving cells for driving the loop is implemented. Each driving cell in the loop is arranged between two branches of the loop. For each driving cell, the loop is opened a plurality of times per driving cell, with one open at a time. A dedicated arrival time of a signal at each sink of the repeater network for the one open at a time per driving cell is calculated. The dedicated arrival time is stored. The calculation step and the storing step is repeated until the dedicated arrival time at each sink of the repeater network is available for each of the opens per driving cell.

Method and system for calculating timing delay in a repeater network in an electronic circuit

A method comprises determining gate configuration from a standard cell library for optimizing behavior of a logic gate in an electronic circuit to be resized. The determining includes defining variables for the logic gate to be resized and defining nets influenced by the logic gate to be resized. The determining includes determining constraints relative to other logic gates in the electronic circuit affected by the logic gate to be resized and formulating objective function. The determining includes solving the objective function using a linear programming solver based on the defined variables and the determined constraints. The determining includes outputting solving of the objective function obtained by linear programming solver for further processing. The gate configuration is selected from the standard cell library for optimizing behavior of the logic gate to be resized based on solving of the objective function.

Gate configuration determination and selection from standard cell library

A method comprises estimating power consumption of an electronic circuit. The estimating includes assigning a first gate of the at least one gate into a priority queue based on a levelized result of the electronic circuit for a full circuit calculation and assigning a second gate of the at least one gate into the priority queue which fan-out gate is directly connected to a fan-in gate of a resized gate for an incremental circuit calculation. The estimating includes, for each gate from the priority queue, performing the following operations. Latest and earliest signal arrival times at an output net of the gate are determined by static timing analysis and calculating a glitch window as difference, and a transition metric is calculated for the output net based on the glitch window. The operations include determining an upper bound of signal transitions, and estimating the power consumption based on the upper bound.

Estimating power consumption of an electronic circuit

A signal repowering chip comprises an input; at least one inverter connected in series to the input; and at least one switch connected to a test enable signal, the at least one switch configured to allow a signal connected to the input to propagate through the at least one inverter in the event that the test enable signal is on. A 3-dimensional integrated circuit comprises a first chip, the first chip comprising a default voltage level and a plurality of wiring layers; and a second chip, the second chip comprising at least one repeater, the repeater being connected to the default voltage level.

Signal repowering chip for 3-dimensional integrated circuit

The present invention relates to a method and respective system for operating a DRAM main memory. One buffer line is provided for multiple pages. When writing data to the buffer it is decided which to which buffer-line the data is written to based on its destination main memory address. A tuple consisting of lower memory address and data is stored. Data entered into the buffer-line will be sorted by page in case the line is flushed to the main memory. Sorting the buffer entries results in less page openings and closings, since the data is re-arranged by memory address and therefore in logical order. By using one line for multiple pages only a fraction of memory of a common set-associative cache is needed, thus decreasing the amount of overhead significantly.

Write buffer for improved DRAM write access patterns

A method comprises reducing power consumption of an electronic circuit, wherein the electronic circuit comprises at least one logic cone with at least one gate having a single output net, wherein representations of the at least one gate are instances of elements from a standard cell library. Reducing of the power consumption comprises determining an upper bound for dynamic power consumption by calculating transition metrics and power metrics for each gate. Reducing of the power consumption comprises selecting gates with an upper bound for power consumption greater than a predetermined threshold value. For each selected gate, performing operations comprising: testing multiple configurations from the standard cell library for the selected gate by calculating respective upper bound for power consumption for each of the multiple configurations; selecting gate configuration with minimum upper bound for power consumption; and modifying the gate-level design representation according to the selected gate configuration.

Glitch power reduction

First and second sets of numbers are received in an input range, which is separated into sub ranges. A first sub range is processed by initializing bits of a memory to a first logical state and by changing the initial state of each of the bits corresponding to a received number of the first set that is within the first sub range. Each number received in the second set is compared to a bit in the memory to identify a set of received numbers that are in the first sub range and that are in both the first set and the second set. The comparing is responsive to detecting a change of initial state of any bit in the memory during the processing of the first sub range. The processing and comparing is repeated for remaining sub ranges to identify received numbers that are in both the sets.

Computing intersection of sets of numbers

An integrated circuit including a first wire of a first level of wiring tracks, a second wire of a second level of wiring tracks, a third wire of a third level of wiring tracks, and a fourth wire located at a first distance from the second wire in the second level of wiring tracks. A first via connects the first and second wires at a first location of the second wire. A second via connects the second and third wires at the first location, the second via is approximately axially aligned with the first via. A third via connecting the third and fourth wires at a second location of the fourth wire. A fourth via connecting the first and fourth wires at the second location, the fourth via is approximately axially aligned with the third via. The second, third, and fourth vias, and the third and fourth wires form a path between the first and second wires redundant to the first via.

Redundant micro-loop structure for use in an integrated circuit physical design process and method of forming the same

A design structure for reducing coupling between wires of an electronic circuit is proposed, wherein sets of nets are classified according to their coupling characteristics, and spacing between wires assigned to the sets of nets is chosen according to the coupling characteristics.

Structure for an integrated circuit design for reducing coupling between wires of an electronic circuit

The invention relates to a delay calculation method for wiring nets of an electronic circuit, wherein a net within an electronic circuit comprises a driver pin and a receiving pin being coupled by at least one loop, the loop comprising a first branching path and a second branching path electrically parallel to the first branching path, wherein at least a first and a second branching point connect the branching paths. The method comprises the steps of disconnecting each branching path once at a time at a specific point in said the at least one loop which connects a driver to at least one specific receiving pin; calculating a delay value of a signal connection between the driver pin and each of the receiving pin for each of the disconnected branching paths of each loop; storing maximum and/or minimum calculated delay values; and applying at least one of the delay values for static timing analysis of the electronic circuit.

Routing of wires of an electronic circuit

The invention relates to a method and a system for placing electric circuits in integrated circuit chip design. Specifically, the invention encompasses performing a global placement step placing the cells into bins on the chip, as well as a detailed placement process which arranges the cells in the bins to obtain a legal arrangement while generating simply connected free space for routing channels.

Method and system for placement of electric circuit components in integrated circuit design

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Weil im Schoenbuch, Germany

Markus Buehler