Nordic Semiconductor Asa

Markus Bakka Hjerto

Arne Wanvik Venas

Frank Berntsen

Per Carsten Skoglund

Asmund Holen

Asghar Havashki

A system () for transferring a data signal (sig_fast) from a first clock domain () to a second clock domain (). The first clock domain () has a first clock (ck_fast) with a frequency greater than the frequency of a second clock (ck_slow) in the second clock domain (). The system () also has a signal input () for receiving an input signal (sig_fast) from the first clock domain (), means () for checking whether the second clock (ck_slow) is in a part of its cycle away from a forthcoming transition, and means () for transferring the input signal (sig_fast) to the second clock domain () if the checking means () determines that the second clock (ck_slow) is in part of its cycle away from a forthcoming transition. The checking means () are clocked by the first clock (ck_fast).

Data transfer between clock domains

An arrangement for transferring a data signal (data_a) from a first clock domain () to a second clock domain () in a digital system. The arrangement has a signal input () for receiving an input signal (data_a) from the first clock domain (), means () for storing the input signal (data_a), and means () for transferring the input signal (data_a) to the second clock domain () following a transition in the clock signal (ck) of the second clock domain ().

An arrangement for transferring a data signal from a first clock domain (bus_slow) to a second clock domain (bus_fast) in a digital system. The first clock domain (bus_slow) has a first clock (ck slow) with a frequency less than a frequency of a second clock (ck fast) in the second clock domain (bus_fast). The arrangement is configured to transfer the data signal from the first clock domain (bus_slow) to the second clock domain (bus_fast), detect whether a predetermined transition occurs in the first clock (ck slow) within a predetermined period of time, using detecting means () clocked by the second clock (ck fast), and transfer the data signal from the first clock domain (bus_slow) to the second clock domain (bus_fast) again if the detecting means () detects the predetermined transition in the first clock (ck slow) within the predetermined period of time.

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Oslo, Norway

Markus Bakka Hjerto