Marvell Asia Pte., Ltd.

Marvell International Limited

Marvellworld Trade Ltd.

Markus Althoff

Xiongzhi Ning

Manfred Kunz

Steffen Dolling

Biing Long Shu

Thomas Kniplitsch

Devin Gharibian-Saki

Frank Viehweg

Sudong Yu

Peter Weber

A network switch, for use in an Ethernet network in a vehicle, includes multiple ports, a switch unit, a peripheral bus, multiple DMA engines and a mapping engine. The ports connect to the Ethernet network. The switch unit forwards packets s among the ports. The peripheral bus connects to a host that runs host applications. The DMA engines transfer packets from the host applications via the peripheral bus to the switch unit. The mapping engine constructs a mapping that maps between (i) bus functions of the peripheral bus that are assigned to the host applications, and (ii) respective ones of the DMA engines, and configures the switch unit, in accordance with the mapping, to permit forwarding of a packet sent from a host application only upon verifying that a DMA engine that transferred the packet is mapped to the bus function assigned to the host application.

Automotive network switch with attack protection

A network switch includes a data bus, a register, an endpoint controller and a direct memory access controller. The endpoint controller is configured to receive a descriptor generated by a device driver of a host system, store the descriptor in the register, and transfer data between a root complex controller of the host system and the data bus. The descriptor identifies an address of a buffer in a memory of the host system. The direct memory access controller is configured to receive the address of the buffer from the endpoint controller or the register and, based on the address and an indication generated by the device driver, independently control transfer of the data between the memory of the host system and a network device connected to the network switch. The direct memory access controller is a receive direct memory access controller or a transmit direct memory access controller.

Network switch with DMA controller for independent direct memory access of host system

Network switch with endpoint and direct memory access controllers for in-vehicle data transfers

A bridge includes buses, a memory, a component module, an interface and an interrupt module. The component module transfers data between a host control module and a network device via the memory and the buses. The interface is connected between the memory and the network device and transmits status information to the memory via one of the buses. The status information indicates completion of a last data transfer between the network device and the host control module. An interrupt module, subsequent to the status information being transmitted to the memory, detects a first interrupt generated by the network device, and transmits an interrupt message to the component module via the memory and the one of the buses. The component module then generates a second interrupt detectable by the host control module. The second interrupt indicates completion of data transfer between the network device and the host control module.

Interrupt handling systems and methods for PCIE bridges with multiple buses

Devices, systems, methods, and other embodiments associated with a network device for interfacing a host with a network are described. One example network device includes a transmit path, and a receive path. A loopback path connects the transmit path and the receive path. A frame detection logic is configured to monitor network traffic on the transmit path to identify loopback frames. When a loopback frame is detected, a loopback logic routes the identified loopback frame onto the loopback path and then to the receive path. The rerouted loopback frame may then be received by a host or an embedded client from the receive path.

Interfacing messages between a host and a network

An apparatus having corresponding methods and computer programs comprises a memory comprising a plurality of locations each to store a node for a binary tree comprising a plurality of the nodes; a classifier to search the tree, wherein the classifier requires one node processing interval to process one of the nodes; and a processor to modify the tree, wherein the processor (a) modifies a pointer that indicates a first one of the nodes to not indicate the first one of the nodes instead, wherein a second one of the nodes is a descendant of the first one of the nodes and is separated from the first one of the nodes by N pointers, (b) waits at least N+1 node processing intervals after (a), and (c) after (b), modifies a pointer that indicates the second one of the nodes to not indicate the second one of the nodes instead.

Growing community of inventors

Achern, Germany

Markus Althoff