Infineon Technologies Dresden Gmbh

Infineon Technologies Ag

Infineon Technologies Austria Ag

Infineon Technologies Dresden Gmbh & Co . Kg

Marko Lemke

Stefan Tegen

Rolf Weis

Anton Mauder

Helmut Strack

Uwe Rudolph

Ralf Rudolf

Dieter Kaiser

Martin Bartels

Kurt Sorschag

Felix Braun

Marcel Heller

Peter Brockhaus

Daniel Sarlette

Ingo Meusel

Jirko Lohse

Mirko Vogt

Ludwig Heitzer

Knut Stahrenberg

Hans Ehm

Claudius Von Petersdorff-Campen

A method for forming a battery element includes etching trenches into a substrate and crystal orientation dependent etching of the trenches. Further, the method includes forming solid state battery structures within the trenches.

Method for forming a battery element, a battery element and a battery

A memory circuit includes a memory element which includes a first electrode layer including lithium. The memory element further includes a second electrode layer and a solid-state electrolyte layer arranged between the first electrode layer and the second electrode layer. The memory circuit also includes a memory access circuit configured to determine a memory state of the memory element.

Memory circuits and a method for forming a memory circuit

According to various embodiments, an integrated circuit structure may include: an electronic circuit being arranged on a surface of a carrier; and a solid state electrolyte battery being at least partially arranged within the carrier, wherein at least a part of the solid state electrolyte battery being arranged within the carrier is overlapping with the electronic circuit along a direction parallel to the surface of the carrier.

Integrated circuit structure and a battery structure

A semiconductor device includes a semiconductor substrate having a first side, and a trench structure having a bottom and a sidewall. The bottom has at least first and second bottom portions laterally adjacent to one another. Each bottom portion has a concave shape with a ridge formed between the first and second bottom portions. An insulating material covers the sidewall and first bottom portion of the trench structure while leaving the second bottom portion uncovered. A mesa region extends to the first side of the substrate and forms the sidewall of the trench structure. The device also includes a first silicide layer on a top region of the mesa region, a second silicide layer on the second bottom portion of the trench structure, a first metal layer on and in contact with the first silicide layer, and a second metal layer on and in contact with the second silicide layer.

Semiconductor device having silicide layers

A method for manufacturing a plurality of nanowires, the method including: providing a carrier comprising an exposed surface of a material to be processed and applying a plasma treatment on the exposed surface of the material to be processed to thereby form a plurality of nanowires from the material to be processed during the plasma treatment.

Apparatus comprising a plurality of nanowires

A semiconductor battery includes a substrate, a battery anode semiconductor material arranged in or over the substrate, a battery cathode material arranged in or over the substrate and a battery electrolyte disposed between the battery anode semiconductor material and the battery cathode material. An electrically insulating encapsulant has a first face and a second face. The substrate is at least partly embedded in the encapsulant. An anode electrode is electrically connected to the battery anode semiconductor material and is disposed over the second face of the encapsulant. A cathode electrode is electrically connected to the battery cathode material and is disposed over the first face of the encapsulant.

Semiconductor battery and semiconductor device including a semiconductor battery

A battery, a battery element and a method for forming a battery element are provided. In an embodiment, a battery element includes a substrate with a plurality of trenches extending into the substrate, wherein a part of a trench of the plurality of trenches is filled with a solid state battery structure, and wherein the trench of the plurality of trenches comprises a cavity.

Battery, a battery element and a method for forming a battery

A method of manufacturing a semiconductor device includes: forming a doped region in a semiconductor substrate at a first distance to a main surface plane of the semiconductor substrate, wherein the doped region is a first section of a semiconductor column extending from the main surface plane into the semiconductor substrate; forming an insulator structure surrounding at least a second section of the semiconductor column between the main surface plane and the first section in planes parallel to the main surface plane; removing the second section of the semiconductor column; and forming a contact structure extending from the main surface plane to the doped region, wherein the contact structure includes a fill structure and a contact layer, the contact layer formed from a metal semiconductor alloy and directly adjoining the doped region and the fill structure formed from a metal and/or a conductive metal compound.

Methods of manufacturing a semiconductor device with a buried doped region and a contact structure

A method for processing a carrier may include: forming a plurality of structure elements at least one of over and in a carrier, wherein at least two adjacent structure elements of the plurality of structure elements have a first distance between each other; depositing a first layer over the plurality of structure elements having a thickness which equals the first distance between the at least two adjacent structure elements; forming at least one additional layer over the first layer, wherein the at least one additional layer covers an exposed surface of the first layer; removing a portion of the at least one additional layer to expose the first layer partially; and partially removing the first layer, wherein at least one sidewall of the at least two adjacent structure elements is partially exposed.

Method for processing a carrier

A method for manufacturing a semiconductor device includes providing a semiconductor substrate having a first side. A trench having a bottom is formed. The trench separates a first mesa region from a second mesa region formed in the semiconductor substrate. The trench is filled with an insulating material, and the second mesa region is removed relative to the insulating material filled in the trench to form a recess in the semiconductor substrate. In a common process, a first silicide layer is formed on and in contact with a top region of the first mesa region at the first side of the semiconductor substrate and a second silicide layer is formed on and in contact with the bottom of the recess.

Method for manufacturing a semiconductor device having silicide layers

A method of forming a power semiconductor device includes providing a semiconductor layer of a first conductivity type extending to a first side and having a first doping concentration of first dopants providing majority charge carriers of a first electric charge type in the layer, and forming a deep trench isolation including forming a trench which extends from the first side into the semiconductor layer and includes, in a vertical cross-section perpendicular to the first side, a wall, forming a compensation semiconductor region of the first conductivity type at the wall and having a second doping concentration of the first dopants higher than the first doping concentration, and filling the trench with a dielectric material. The amount of first dopants in the compensation semiconductor region is such that a field-effect of fixed charges of the first electric charge type which are trapped in the trench is at least partly compensated.

Method for forming a power semiconductor device and a power semiconductor device

A semiconductor device includes a buried doped region at a first distance to a main surface of a semiconductor body. A contact structure extends from the main surface to the doped region. The contact structure includes a contact layer formed from a metal-semiconductor alloy that directly adjoins the doped region. The contact structure further includes a fill structure formed from a metal or a conductive metal compound. An insulator structure surrounds the contact structure in cross-sections parallel to the main surface.

Semiconductor device with buried doped region and contact structure

A battery element includes a substrate with a plurality of trenches extending into the substrate. At least a part of each trench of the plurality of trenches is filled with a solid state battery structure. Further, the battery element includes a front side battery element electrode arranged at a front side of the substrate and electrically connected to a first electrode layer of the solid state battery structures within the plurality of trenches. Additionally, the battery element includes a backside battery element electrode arranged at a backside of the substrate and electrically connected to a second electrode layer of the solid state battery structures within the plurality of trenches.

Battery element, a battery and a method for forming a battery

According to various embodiments, an electronic structure may be provided, the electronic structure may include: a semiconductor carrier, and a battery structure monolithically integrated with the semiconductor carrier, the battery structure including a plurality of thin film batteries.

Electronic structure, a battery structure, and a method for manufacturing an electronic structure

A method for forming a semiconductor device includes providing a semiconductor substrate having an upper side and comprising, in a vertical cross-section substantially orthogonal to the upper side, a plurality of semiconductor mesas of a first monocrystalline semiconductor material which are spaced apart from each other by sacrificial layers selectively etchable with respect to the first monocrystalline semiconductor material and arranged in trenches extending from the upper side into the semiconductor substrate, forming on the semiconductor mesas a support structure mechanically connecting the semiconductor mesas, at least partly replacing the sacrificial layers while the semiconductor mesas remain mechanically connected via the support structure, and at least partly removing the support structure.

Growing community of inventors

Dresden, Germany

Marko Lemke