University of Zagreb Faculty of Electrical Engineering and Computing

Asahi Kasei Microdevices Corporation

Other

Asahi Kasei Emd Corporation

Sveuciliste U Zagrebu Fakultet Elektrotehnike I Racunarstva

Marko Koricic

Tomislav Suligoj

Hidenori Mochizuki

Josip Zilak

Zeljko Osrecki

Soichi Morita

A semiconductor device including a Horizontal Current Bipolar Transistor (HCBT) and methods of manufacture. The device has a semiconductor substrate of a first conductivity type defining a wafer plane parallel to the semiconductor substrate and has a base region and a collector region forming a first metallurgical junction. The device also has an emitter region forming a second metallurgical junction with the base region. A flat portion of the first metallurgical junction and a flat portion of the second metallurgical junction are substantially parallel to each other and close an acute angle with the wafer plane. At least a portion of the base region comprises silicon-germanium alloy or silicon-germanium-carbon alloy.

Horizontal Current Bipolar Transistor with Silicon-Germanium base

Horizontal current bipolar transistor with silicon-germanium base

A horizontal current bipolar transistor comprises; an n-hill layer on a substrate, forming a first pn-junction with the substrate; a n+ diffusion layer on the substrate, adjacent to the n-hill layer, forming a n+n junction with the n-hill layer; an intrinsic base layer on the n-hill layer and comprising a portion of a sidewall inclined at an acute angle to the substrate plane, forming a second pn-junction with the n-hill layer; an extrinsic base layer on the n-hill layer, forming a third pn-junction with the n-hill layer, and a pp junction with the intrinsic base layer; a field limiting region on the n-hill layer, forming a fourth pn-junction with the n-hill layer. The field limiting region is spatially separated from the extrinsic base layer and the n+ diffusion layer. The extrinsic base layer and the field limiting region exhibit substantially equal impurity dopant distribution decay towards the substrate.

Horizontal current bipolar transistor with floating field regions

A horizontal current bipolar transistor comprises a substrate of first conductivity type, defining a wafer plane parallel to said substrate; a collector drift region above said substrate, having a second, opposite conductivity type, forming a first metallurgical pn-junction with said substrate; a collector contact region having second conductivity type above said substrate and adjacent to said collector drift region; a base region comprising a sidewall at an acute angle to said wafer plane, having first conductivity type, and forming a second metallurgical pn-junction with said collector drift region; and a buried region having first conductivity type between said substrate and said collector drift region forming a third metallurgical pn-junction with the collector drift region. An intercept between an isometric projection of said base region on said wafer plane and an isometric projection of said buried region on said wafer plane is smaller than said isometric projection of said base region.

Horizontal current bipolar transistors with improved breakdown voltages

A configuration of a lateral transistor suited for the hybrid-integration (BiCMOS) of a high-performance lateral transistor (HCBT) and a CMOS transistor, and a method for manufacturing the lateral transistor. A semiconductor device includes a HCBTand a CMOS transistorhybrid-integrated. The HCBThas an open regionopened by etching a device isolating oxide filmsurrounding an n-hill layer. An emitter electrodeA and a collector electrodeB are formed in the open regionand are composed of a polysilicon film having such a thickness as to expose the n-hill layerexposed by etching the device isolating oxide film, and an ultrathin oxide filmcovering at least a part of the n-hill layer. The ultrathin oxide filmfunctions as a protective film for protecting the n-hill layerfrom being etched when the polysilicon film is etched.

Semiconductor device comprising a lateral bipolar transistor

A configuration of a lateral transistor suited for the hybrid-integration (BiCMOS) of a high-performance lateral transistor (HCBT) and a CMOS transistor, and a method for manufacturing the lateral transistor are provided. A semiconductor device includes a HCBTand a CMOS transistorhybrid-integrated therein. The HCBThas an open regionopened by etching a device isolating oxide filmsurrounding an n-hill layer, an emitter electrodeA and a collector electrodeB each of which is formed in the open regionand is composed of a polysilicon film having such a thickness as to expose the n-hill layerexposed by etching the device isolating oxide film, and an ultrathin oxide filmcovering at least a part of the n-hill layer. The ultrathin oxide filmfunctions as a protective film for protecting the n-hill layerfrom being etched when the polysilicon film is etched to form the emitter electrodeA and the collector electrodeB.

Growing community of inventors

Zagreb, Croatia

Marko Koricic