USA As Represented by Secretary of the Navy

University of California

Northrop Grumman Systems Corporation

Marko J Tadjer

Karl D Hobart

Travis J Anderson

Andrew D Koehler

Tatyana I Feygelson

Francis J Kub

Boris N Feigelson

Robert E Stahlbush

Mark Goorsky

Nadeemullah A Mahadik

Samuel Graham, Jr

Michael Anthony Mastro

Joshua D Caldwell

Eugene A Imhoff

Alan G Jacobs

Bradford B Pate

James C Gallagher

Luke Yates

Tingyu Bai

Asif Khan

Yekan Wang

Lunet E Luna

Zhe Cheng

Jordan D Greenlee

Virginia D Wheeler

Vincent Gambin

Orest J Glembocki

Ioulia Smorchkova

James E Butler

Gregory Todd Lewis

Rajinder S Sandhu

Eugene I Imhoff

David Shahin

Jeff McKay

Kendrick X Liu

Semiconductor heterostructures having an engineered polarization. Semiconductor materials having specified crystallographic directions and specified polarizations are directly bonded to one another by means of atomic layer bonding without the use of any interfacial bonding materials, where spontaneous polarization of the two layers produced by joining the two materials by direct wafer bonding produces a strong 2DEG or 2DHG at the interface. Embodiments include GaN/AlN and AlN/GaN heterostructures having an N- or Ga-polar GaN layer directly bonded to an N- or Al-polar Al layer. Other embodiments can incorporate an InN epitaxial layer or an alloy incorporating an N-polar, Al-polar, or Ga-polar material having In, Al, or Ga in the crystal lattice, e.g., (InAlN), InGaN, AlGaN, InAlGaN, where (0<x≤1, 0<y≤1, 0<x+y≤1).

Polarization-engineered heterogeneous semiconductor heterostructures

Methods for obtaining a free-standing thick (>5 μm) epitaxial material layer or heterostructure stack and for transferring the thick epitaxial layer or stack to an arbitrary substrate. A thick epitaxial layer or heterostructure stack is formed on an engineered substrate, with a sacrificial layer disposed between the epitaxial layer and the engineered substrate. When the sacrificial layer is removed, the epitaxial layer becomes a thick freestanding layer that can be transferred to an arbitrary substrate, with the remaining engineered substrate being reusable for subsequent material layer growth. In an exemplary case, the material layer is a GaN layer and can be selectively bonded to an arbitrary substrate to selectively produce a Ga-polar or an N-polar GaN layer.

Transferring large-area group III-nitride semiconductor material and devices to arbitrary substrates

A method for activating implanted dopants and repairing damage to dopant-implanted GaN to form n-type or p-type GaN. A GaN substrate is implanted with n- or p-type ions and is subjected to a high-temperature anneal to activate the implanted dopants and to produce planar n- or p-type doped areas within the GaN having an activated dopant concentration of about 10-10cm. An initial annealing at a temperature at which the GaN is stable at a predetermined process temperature for a predetermined time can be conducted before the high-temperature anneal. A thermally stable cap can be applied to the GaN substrate to suppress nitrogen evolution from the GaN surface during the high-temperature annealing step. The high-temperature annealing can be conducted under Npressure to increase the stability of the GaN. The annealing can be conducted using laser annealing or rapid thermal annealing (RTA).

GaN devices with ion implanted ohmic contacts and method of fabricating devices incorporating the same

A method for growing polycrystalline diamond films having engineered grain growth and microstructure. Grain growth of a polycrystalline diamond film on a substrate is manipulated by growing the diamond on a nanopatterned substrate having features on the order of the initial grain size of the diamond film. By growing the diamond on such nanopatterned substrates, the crystal texture of a polycrystalline diamond film can be engineered to favor the preferred &#x3c;110&#x3e; orientation texture, which in turn enhances the thermal conductivity of the diamond film.

Diamond on nanopatterned substrate

Current conducting devices and methods for their formation are disclosed. Described are vertical current devices that include a substrate, an n-type material layer, a plurality of p-type gates, and a source. The n-type material layer disposed on the substrate and includes a current channel. A plurality of p-type gates are disposed on opposite sides of the current channel. A source is disposed on a distal side of the current channel with respect to the substrate. The n-type material layer comprises beta-gallium oxide.

Heterojunction devices and methods for fabricating the same

A method of cleaving includes providing a substrate. Optionally, the substrate includes &#x3b2;-gallium oxide, hexagonal zinc sulfide, or magnesium selenide. The substrate includes at least one natural cleave plane and a crystallinity. The substrate is cleaved along a first natural cleave plane of the at least one natural cleave plane. The cleaving the substrate along the first natural cleave plane includes the following. A micro-crack is generated in the substrate while maintaining the crystallinity adjacent to the micro-crack by generating a plurality of phonons in the substrate, the micro-crack comprising a micro-crack direction along the first natural cleave plane. The micro-crack is propagated along the first natural cleave plane while maintaining the crystallinity adjacent to the micro-crack. Optionally, generating a micro-crack in the substrate by generating a plurality of phonons in the substrate includes generating the plurality of phonons by electron-hole recombination. Optionally, the electron-hole recombination includes non-radiative electron-hole recombination.

UV laser slicing of &#x3b2;-GaOby micro-crack generation and propagation

A device structure and method for improving thermal management in highly scaled, high power electronic and optoelectronic devices such as GaN FET and AlGaN/GaN HEMT devices by implementing diamond air bridges into such devices to remove waste heat. The diamond air bridge can be formed from a polycrystalline diamond material layer which can be grown on the surface of a dielectric material layer, on the surface of a III-nitride material, or on the surface of a diamond polycrystalline nucleation layer, and may be optimized to have a high thermal conductivity at the growth interface with the underlying material.

Diamond air bridge for thermal management of high power devices

A method for removing existing basal plane dislocations (BPDs) from silicon carbide epilayers by using a pulsed rapid thermal annealing process where the BPDs in the epilayers were eliminated while preserving the epitaxial surface. This high temperature, high pressure method uses silicon carbide epitaxial layers with a carbon cap to protect the surface. These capped epilayers are subjected to a plurality of rapid heating and cooling cycles.

Basal plane dislocation elimination in 4H&#x2014;SiC by pulsed rapid thermal annealing

A method and device including adding a protective layer on the surface of a substrate, annealing the substrate at a temperature approximately greater or equal to 1850&#xb0; C., removing the protective layer from the surface of the substrate after the annealing, and growing a first epilayer on the substrate after the removing of the protective layer, wherein the first epilayer is grown without attempting to prevent the basal plane dislocations to propagate in the first epilayer when growing the first epilayer, and wherein the first epilayer is free of the basal plane dislocations.

Removal of basal plane dislocations from silicon carbide substrate surface by high temperature annealing and preserving surface morphology

Growing community of inventors

Springfield, VA, United States of America

Marko J Tadjer