Nokia Telecommunications Oy

Nokia Corporation

Nokia Networks Oy

Intellectual Ventures I LLC

Markku Ruuskanen

Reijo Leppanen

Antti Tuominen

Tapio Kallioniemi

Ari Hurtta

The present invention relates to a method and a system of implementing a signal processing facility in a digital transmission system environment. In the invention, the signal between the switching field (GSW) and the interface unit ETS1 is divided into a first (DEOS, DSOE) and second signal (DGO, DSO). The first signal is directed through the signal processing unit and the second signal past it. Either one of the signals is selected and activated depending on the need of the signal processing and the operational status of the signal processing unit; this information the interface unit gets from the control unit.

Method and system for processing telecommunication signals

The invention concerns a function taking place in a digital phase lock, when it is desired to exchange a synchronization signal supplied to the phase lock for another synchronization signal. Using a cut-off circuit, the phase difference between a selected reference signal and a signal formed by dividing from an oscillator signal is set with time constant accuracy at the setting value for the phase difference. The method according to the invention, then uses as phase setting value the current value of the phase difference obtained by cut-off connection. Thus, the method according to the invention begins using a reference signal-specific setting value instead of a fixed setting value. Since the setting value is determined adaptively in accordance with the signal of the synchronization source used at each time, no phase transfer will occur during the change.

Control of phase locked loop during change of synchronization source

The invention relates to a redundant switching arrangement using a first and second switching network (SWF_A, SWF_B) or other switching element. The switching elements are used to carry out switching operations in the same way, so that one of the switching elements serves as an active switching element whose switching operations are utilised, while the other switching element serves as a passive switching element backing up the active switching element. To ensure that any faults occurring in the switching elements in such a redundant switching arrangement are detected as quickly as possible, their operation is monitored by comparing the data of the corresponding output channels of the first and second switching elements, and if such a comparison shows that the data contained in any of the corresponding output channels are not identical, an internal test is carried out for at least one of the switching elements to verify the data of the output channel involved. The internal compare test(s) is/are used as a basis for selecting the switching element to continue to serve as the active switching element.

Redundant switching arrangement

The invention relates to implementing switching in a switch in a digital telecommunications system. N incoming signals are introduced to the switch, each comprising successive one-bit time slots that form successive frames each comprising K time slots. The contents of the time slots for the incoming signals are stored in a memory at a memory location determined by a write address in such a way that a word having the width of at least one bit is stored at one memory location. One word at a time is read out from the memory, wherefrom the desired bit is selected for the outbound signal from the switch. To optimize the size and power consumption of the switch, the incoming signals are distributed to X multiplexers (A,. . . A,), each interleaving the incoming signals thereto into a single serial output signal (IN,. . . INX), and writing into memory is carried out by writing the contents of the time slots of the output signals into the same memory location having a width of at least X bits, the memory location changing from one time slot of the output signals of the multiplexers to another.

Switch with one-bit resolution

Method and system for automatic compensation of line delay in a clock

Method and device for symmetrizing a clock signal

A method and circuit in which one of at least two asynchronous constant frequency input clock signals is selected for being used as an output clock signal by use of a separate selection signal for providing redundancy for an asynchronous clock signal.

Growing community of inventors

Porvoo, Finland

Markku Ruuskanen