Emc Corporation

Mark Zani

John K Walton

Christopher S MacLellan

William R Tuccio

Robert A Thibault

Ofer Porat

Paul C Wilson

Farouk Khan

Alexander Rabinovich

Scott Romano

Michael S Gadarowski

Charles S Loewy

Steven MacArthur

Kendall A Chilton

Alfred Dellicicchi

Thomas Georgens

A system interface includes a plurality of first directors, a plurality of second directors, a data transfer section and a message network. The data transfer section includes a cache memory. The cache memory is coupled to the plurality of first and second directors. The messaging network operates independently of the data transfer section and such network is coupled to the plurality of first directors and the plurality of second directors. The first and second directors control data transfer between the first directors and the second directors in response to messages passing between the first directors and the second directors through the messaging network to facilitate data transfer between first directors and the second directors. The data passes through the cache memory in the data transfer section. A method for operating a data storage system adapted to transfer data between a host computer/server and a bank of disk drives. The method includes transferring messages through a messaging network with the data being transferred between the host computer/server and the bank of disk drives through a cache memory, such message network being independent of the cache memory.

Data storage system having point-to-point configuration

A system analyzer for a data storage system has a control module and a memory module. The system analyzer includes a logic analyzer, an input port that couples to the data storage system, an output port that couples to the logic analyzer, and a pre-processor which is interconnected between the input port and the output port. The pre-processor is configured to receive, while a first point-to-point signal is exchanged between the control module and the memory module, a second point-to-point signal which is a copy of the first point-to-point signal. The pre-processor is further configured to generate a pre-processed signal based on the second point-to-point signal, and to provide the pre-processed signal to the logic analyzer.

System analyzer for a data storage system

A data storage system wherein a host computer is coupled to a bank of disk drives through a system interface. The interface has a memory with a high address memory section and a low address memory section. A plurality of directors control data transfer between the host computer and the bank of disk drives as such data passes through the memory. A pair of high address busses electrically is connected to the high address memory and a pair of low address busses is electrically connected to the low address memory. Each one of the directors is electrically connected to one of the pair of high address busses and one of the pair of low address busses. A front-end portion of the directors is electrically connected to the host computer and a rear-end portion of the directors is electrically connected to the bank of disk drives. The bank of disk drives has a plurality of sets of electrically connected disk drives, each one of the sets being connected to a corresponding one of the input/output interfaces of a corresponding one of the rear-end directors through the adapter card connected to such corresponding one of the rear-end directors and, through the printed circuit board, to the adapter card in the another one of the electrical connectors and to the input/output interface of the rear-end director in such other one of the electrical connectors. Each pair of a plurality of bus arbiters is electrically connected to ends of a corresponding one of the busses. One of the arbiters is a master arbiter and the other a slave arbiter. A pair of reference voltage generator is also connected to ends of each bus.

Data storage system having master-slave arbiters

A data storage system wherein a host computer is coupled to a bank of disk drives through a system interface. The system interface includes a memory having a high address memory section and a low address memory section. A plurality of directors controls data transfer between the host computer and the bank of disk drives as such data passes through the memory. A pair of high address busses, comprising a plurality of bus high address bus segments, is in communication with the high address memory section and a pair of low address busses, comprising a plurality of low address bus segments, is in communication with the low address memory section. Each one of the directors is in communication with one of the pair of high address busses and one of the pair of low address busses.

Large capacity data storage systems using redundant buses

A peripheral device interface is coupled between a computer system bus and a peripheral bus. The peripheral device bus includes a signal line which can be configured in either a single-ended or a differential configuration. A peripheral controller is coupled to the computer system bus. A single-ended signal line interface circuit is coupled between the peripheral bus signal line and the peripheral controller, and may be selectively enabled in response to a control signal. A differential signal line interface circuit is also coupled between the peripheral bus signal line and the peripheral controller and also may be selectively enabled in response to a control signal. The peripheral controller generates the control signals for the single-ended signal line interface circuit and the differential signal line interface circuit. Those control signals enable the single-ended signal line interface circuit when the peripheral bus signal line is a single-ended signal line and enable the differential signal line interface circuit when the peripheral bus signal line is a differential signal line.

System for automatically terminating a daisy-chain peripheral bus with

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Derry, NH, United States of America

Mark Zani