Trw Limited

Northrop Grumman Systems Corporation

Mark Winslow Johnson

Quentin P Herr

Dale J Durand

Bruce J Dalrymple

Arnold H Silver

Andrew Donovan Smith

James T Hall

James A Roth

Larry R Eaton

Craig R Wilkinson

Dennis G Neal

Steven Lai

A passive thermal control blanket and a method for its manufacture, the blanket including a plastic substrate on which is deposited a film that is a homogeneous mixture of silicon and germanium, thereby combining the excellent reflective and electrostatic discharge properties of germanium with the superior adhesion and corrosion resistance properties of silicon. The uniform mixture is preferably obtained by sputtering the two materials simultaneously onto the substrate, using either separate targets, a single mosaic target, or a single composite target.

Mixed germanium-silicon thermal control blanket

An on-chip current regulator for a superconducting logic circuit isolates the superconducting logic circuit from external noise, reduces the effects of process fluctuations on the performance of the logic circuit and significantly reduces total circuit power requirements. The on-chip current regulator in accordance with the present invention includes one or more hysteretic Josephson junctions each connected in parallel with a resistor forming a resistively shunted junction (RSJ) or includes a self-shunting junction. One RSJ may be coupled between an off-chip current regulator and the hysteretic Josephson junction that functions as a current limiting resistor and provides improved isolation from external noise. One or more RSJs may be coupled between the hysteretic Josephson junction and the superconducting logic circuit which functions as a biasing resistor but at the same time reducing the sensitivity of the superconducting logic circuit to any process fluctuations in the biasing resistor which improves manufacturing yield. In an alternate embodiment of the invention, one or more RSJs can be used in place of the RSJ and the biasing resistor. In another alternate embodiment of the invention, the current regulator is formed from an RSJ and a serially coupled damping impedance.

Superconducting constant current source

A superconducting oscillator/counter analog-to-digital converter ( ) that provides simultaneous in-phase and quadrature-phase of an RF input signal. The RF input signal is converted to a series of SFQ input pulses by a superconducting voltage controlled oscillator ( ). A clock circuit ( ) generates a series of SFQ clock pulses. The SFQ input pulses and the SFQ clock pulses are applied to a pulse repulsion circuit ( ) that outputs the SFQ input pulses and the SFQ clock pulses spaced apart in time. In one embodiment, the pulse repulsion circuit ( ) includes two Josephson transmission lines ( ), where the magnetic coupling between the lines ( ) provides the SFQ pulse repulsion.

Application of single flux quantum pulse interaction to the simultaneous sampling in-phase and quadrature analog-to-digital converter

A Josephson junction transmission line ( ) for transmitting single flux quantum pulses. The transmission line ( ) includes a current source ( ), a plurality of isolation inductors ( ) electrically coupled in series along the transmission line ( ), and a plurality of Josephson junction circuits ( ) electrically coupled in parallel along the transmission line ( ). Each of the Josephson junction circuits ( ) includes only a Josephson junction ( ) and a parasitic inductor ( ) coupled in series. The Josephson junction circuits ( ) do not include a damping resistor in order to reduce timing uncertainty and to enhance propagation speed.

Underdamped Josephson transmission line

A superconductor circuit ( ) for providing active timing arbitration between SFQ pulses. The superconductor circuit ( ) includes a first superconducting transmission line ( ) having at least one inductor ( ) for transmitting first input pulses, and a second superconducting transmission line ( ) having at least one inductor ( ) for transmitting second input pulses that are correlated to the first input pulses. The first and second superconducting transmission lines ( ) are coupled together in order to generate a flux attraction between the first and second input pulses for reducing relative timing uncertainty.

Active timing arbitration in superconductor digital circuits

The level of bias current ( ) required by a superconductor integrated circuit ( & ) is lowered by separating the circuit into portions having separate ground planes and supplying the bias current to the circuit portion ( ) in one ground plane in series ( ) with that for the circuit portion ( ) in another ground plane. To maintain DC isolation between those circuit portions, SFQ pulses inputted (SFQ IN) move across the separate ground planes through a pair of inductively coupled SQUIDS ( & ) that define a DC transformer; and a combiner ( ) reconstitutes and outputs the SFQ pulses. To provide inductive coupling the DC transformer includes a primary ( ) and isolated secondary ( ) winding.

Single flux quantum series biasing technique using superconducting DC transformer

A superconducting A/D converter ( ) has an error correction system ( ) for eliminating non-linearities in a primary quantizer ( ). The converter ( ) includes a primary quantizer ( ), a primary SFQ counter ( ), and the error correction system ( ). The primary quantizer ( ) generates primary SFQ pulses based on an average voltage of an analog input signal. The primary SFQ counter ( ) converts the primary SFQ pulses into a digital output signal based on a frequency of the primary SFQ pulses. The error correction system ( ) corrects the digital output signal based on the analog input signal and the primary SFQ pulses. Using the primary SFQ pulses to correct the digital output signal allows the converter ( ) to take into account the non-linearities of the primary quantizer ( ).

Gated counter analog-to-digital converter with error correction

A receiver ( ) for providing chip-to-chip communication in a superconductor integrated circuit. The receiver ( ) includes a detector circuit ( ) for asynchronously receiving an input current, a splitter circuit ( ) connected to the detector circuit ( ) for generating first and second signals, a delay circuit ( ) receiving the second signal from the splitter circuit for generating a delayed signal and a register circuit ( ) receiving the first signal from the splitter circuit ( ) and the delayed signal from the delay circuit ( ) for producing a single flux quantum (SFQ) pulse. The receiver ( ) according to the present invention provides an asynchronous chip-to-chip communication between a multi-chip superconductive circuit having low input current without an external rf clock.

High-sensitivity, self-clocked receiver for multi-chip superconductor circuits

An oscillator/multiply-accumulator AID converter ( ) which simultaneously provides frequency downconversion, band pass filtering and analog-to-digital conversion of an analog signal, where the analog signal includes a carrier wave modulated with information by any known modulation technique. The converter ( ) uses a superconducting, Josephson single flux quantum circuit operating as a voltage controlled oscillator ( ). The voltage controlled oscillator ( ) receives the analog signal to be converted, and generates a series of sharp, high frequency pulses based on the characteristics of the carrier signal. The series of pulses are applied to a gate circuit ( ) that either passes or blocks the pulses depending on a gate control signal ( ). When the pulses are passed by the gate circuit ( ), a multiply-accumulator ( ) multiplies the pulse by a binary coefficient ( ) and accumulates the products ( ) resulting from the multiplication during a predetermined time period. The predetermined time period includes at least one sampling period. Each sample is multiplied by a different weight and their products ( ) are accumulated. This operation eliminates the DC response, and leads to an improved frequency response.

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La Canada Flintridge, CA, United States of America

Mark Winslow Johnson