International Business Machines Corporation

Nvidia Corporation

Mark William Stephenson

Ram Rangan

Lixin Zhang

Elmootazbellah Nabil Elnozahy

Daniel Robert Johnson

Sana Damani

Ramakrishnan Rajamony

Jack H Choquette

Patrick Joseph Bohrer

Michael D Kistler

Michael Patrick McKeown

William Evan Speight

Olivier Giroux

Aamer Jaleel

Michael Brendan Sullivan

Thomas Henry Osiecki

Mohamed Tarek Bnziad Mohamed Hassan

Rishkul Kulkarni

Jan Simon Rellermeyer

Oliver Giroux

Warp sharding techniques to switch execution between divergent shards on instructions that trigger a long stall, thereby interleaving execution between diverged threads within a warp instead of across warps. The technique may be applied to mitigate pipeline stalls in applications with low warp occupancy and high divergence. Warp data cache locality may also be improved by concentrating memory accesses within a warp rather than spreading them across warps.

Techniques for divergent thread group execution scheduling

Convergence of threads executing common code sections is facilitated using instructions inserted at strategic locations in computer code sections. The inserted instructions enable the threads in a warp or other group to cooperate with a thread scheduler to promote thread convergence.

Convergence among concurrently executing threads

While a compiler compiles source code to create an executable binary, code is added into the compiled source code that, when executed, identifies and stores in a metadata table base and bounds information associated with memory allocations. Additionally, additional code is added into the compiled source code that performs memory safety checks during execution. This updated compiled source code automatically determines a safety of memory access requests during execution by performing an out-of-bounds (OOB) check using the base and bounds information retrieved and stored in the metadata table. This enables the identification and avoidance of unsafe memory operations during the implementation of the executable by a GPU.

Implementing compiler-based memory safety for a graphic processing unit

Each of a plurality of stations has a respective sequence of tracks of Internet content of common subject matter and a respective play pointer indicating a location in the sequence of tracks. In response to a first input, the presentation mode of the station is configured in a continuous play mode in which the play pointer is progressed through the sequence of tracks queued to the station regardless of whether or not the station is presently selected for presentation. In response to a second input, the presentation mode is configured in a pause play mode in which the play pointer is progressed through the sequence of tracks queued to the station only while the station is selected for presentation to a user and otherwise pauses progression of the play pointer. The processor transmits tracks of the station and progresses the play pointer in accordance with the configured presentation mode.

Personalized audio presentation of textual information

A technique for handling predicated code in an out-of-order processor includes detecting a predicate defining instruction associated with a predicated code region. Renaming of predicated instructions, within the predicated code region, is then stalled until a predicate of the predicate defining instruction is resolved.

Techniques for predicated execution in an out-of-order processor

A method, system, and computer program product for random number generation using a network of mobile devices are provided in the illustrative embodiments. From a set of mobile devices, a corresponding set of data packets is received. A presence of raw sensor data is detected in a first data packet received from a first mobile device in the set of mobile devices. The raw sensor data comprises data corresponding to changing value of an output of a sensor in a set of sensors installed in the first mobile device. The raw sensor data is separated from the first data packet, resulting in an original data packet. A first random number is generated using the raw sensor data.

Random number generation using a network of mobile devices

A respective sequence of tracks of Internet content of common subject matter is queued to each of a plurality of stations, where each of the tracks of Internet content resides on a respective Internet resource in textual form. In response to receiving a sample input, snippets of each of multiple tracks queued to a selected station among the plurality of stations is transmitted for audible presentation as synthesized human speech, where each of the snippets includes only a subset of a corresponding track. Thereafter, one or more complete tracks among the multiple tracks for which snippets were previously transmitted are transmitted for audio presentation as synthesized human speech.

Variable-depth audio presentation of textual information

A predication technique for out-of-order instruction processing provides efficient out-of-order execution with low hardware overhead. A special op-code demarks unified regions of program code that contain predicated instructions that depend on the resolution of a condition. Field(s) or operand(s) associated with the special op-code indicate the number of instructions that follow the op-code and also contain an indication of the association of each instruction with its corresponding conditional path. Each conditional register write in a region has a corresponding register write for each conditional path, with additional register writes inserted by the compiler if symmetry is not already present, forming a coupled set of register writes. Therefore, a unified instruction stream can be decoded and dispatched with the register writes all associated with the same re-name resource, and the conditional register write is resolved by executing the particular instruction specified by the resolved condition.

Predication supporting code generation by indicating path associations of symmetrically placed write instructions

A mechanism is provided for automatic detection of assertion violations. An application may write assertion tuples to the assertion checking mechanism. An assertion tuple forms a Boolean expression (predicate or invariant) that the developer of the application wishes to check. If the assertion defined by the tuple remains true, then the application does not violate the assertion. For any instruction that stores a value to a memory location or register at a target address, the assertion checking mechanism compares the target address to the addresses specified in the assertion tuples. If the target address matches one of the tuple addresses, then the assertion checking mechanism reads a value from the other address in the tuple. The assertion checking mechanism then recomputes the assertion using the retrieved value along with the value to be stored. If the assertion checking mechanism detects an assertion violation, the assertion checking mechanism raises an exception.

Architectural support for automated assertion checking

A method, computer system, and computer program product for using one or more hardware interrupts to drive dynamic binary code recompilation. The execution of a plurality of instructions is monitored to detect a problematic instruction. In response to detecting the problematic instruction, a hardware interrupt is thrown to a dynamic interrupt handler. A determination is made whether a threshold for dynamic binary code recompilation is satisfied. If the threshold for dynamic code recompilation is satisfied, the dynamic interrupt handler optimizes at least one of the plurality of instructions.

Using hardware interrupts to drive dynamic binary code recompilation

A method, system, and computer usable program product for energy-efficient soft error failure detection and masking are provided in the illustrative embodiments. A soft error is injected to occur during execution of a set of instructions. If an output of the execution of the set of instructions is incorrect, a record is made of the instruction that was affected by the injected soft error and led to the incorrect result. This identified instruction is designated as vulnerable to the soft error. Several soft errors are injected with different input data sets over several executions of the same set of instructions, and a probability of each instruction in the instruction set is computed, the probability of an instruction accounting for the vulnerability of the execution of the instruction sets to errors that affect the instruction. A report including several probabilities of instruction vulnerabilities is produced.

Energy-efficient failure detection and masking

A method, system, and computer usable program product for tolerating soft errors by selective duplication are provided in the illustrative embodiments. An application executing in a data processing system, selects an instruction that has to be protected from soft errors. The instruction is marked for duplication such that the instruction is duplicated during execution of the instruction. The marked instruction is sent for execution to a hardware front end.

Growing community of inventors

Austin, TX, United States of America

Mark William Stephenson