International Business Machines Corporation

Mark William Kapfhammer

Charles Leon Arvin

Thomas Weiss

David Clifford Long

Mark J LaPlante

Brian W Quinlan

Steve Ostrander

Bhupender Singh

Brian Michael Erwin

James G Balz

Charles L Reynolds

Nabil A Rizk

Kamal Kumar Sikka

Lester W Herron

William Dale Carbaugh, Jr

James Robert Wylder

Lawrence Alfred Clevenger

Arvind Kumar

Govindarajan Natarajan

Joshua M Rubin

Jon Alfred Casey

Shidong Li

Thomas Edward Lombardi

Richard Francis Indyk

Lannie R Bolde

Dinesh Gupta

James H Covell

Maryse Cournoyer

Valérie Anne Oberson

Hilton T Toy

Benjamin V Fasano

Sushumna Iruvanti

James N Humenik

Glenn A Pomerantz

Hsichang Liu

Gregg B Monjeau

Jiantao Zheng

Richard D Langlois

Kurt A Smith

Sylvain Pharand

David J Lewison

Joseph C Sorbello

Richard A Shelleman

David H Gabriels

You-Wen Yau

William T Grant

Nirmal S Sandhu

Rachel E Olson

Joseph Jacobi

Mohamad A Sarfaraz

William Cobbett, Jr

Robert H Anders, Jr

An integrated circuit package structure is provided that includes a chip carrier substrate, at least one processor die provided on the chip carrier substrate, a plurality of lateral escape wiring lines connected to and extending away from the at least one processor die, and a plurality of chips at least partially surrounding the processor die, at least one of the chips overlapping with at least one of the lateral escape wiring lines in a plan view. An interconnect structure of the chips includes at least one vertical power feed structure that is configured and positioned not to intersect with the lateral escape wiring lines in the plan view.

Near tier decoupling capacitors

A multi-die integrated circuit device and a method of fabricating the multi-die integrated circuit device involve a substrate. Two or more dice include components that implement functionality of the multi-die integrated circuit. The components include logic gates. The multi-die integrated circuit device also includes a spacer disposed between the substrate and each of the two or more dice. Each of the two or more dice makes direct electrical contact with the substrate without making direct electrical contact with the spacer through holes in the spacer.

Spacer for die-to-die communication in an integrated circuit and method for fabricating the same

An integrated circuit package includes a substrate, a flip chip die, and a capacitor. The flip chip die is attached to the substrate via die-to-substrate interconnects. The capacitor is attached to the flip chip die via capacitor-to-die interconnects so that the capacitor occupies a region between the flip chip die and the substrate. Such placement of the capacitor on a flip chip die has the advantage of reducing the distance between the capacitor and its core, thereby reducing unwanted line inductance and series resistance effects. Integrated circuit performance is thereby enhanced.

Direct attachment of capacitors to flip chip dies

An alignment carrier, assembly and methods that enable the precise alignment and assembly of two or more semiconductor die using an interconnect bridge. The alignment carrier includes a substrate composed of a material that has a coefficient of thermal expansion that substantially matches that of an interconnect bridge. The alignment carrier further includes a plurality of solder balls located on the substrate and configured for alignment of two or more semiconductor die.

Alignment carrier for interconnect bridge assembly

Direct bonding heterogeneous integration packaging structures and processes include a packaging substrate with first and second opposing surfaces. A trench or a pedestal is provided in the first surface. A bridge is disposed in the trench or is adjacent the pedestal sidewall, wherein the bridge includes an upper surface coplanar with the first surface of the package substrate. At least two chips in a side by side proximal arrangement overly the bridge and the packaging substrate, wherein the bridge underlies peripheral edges of the at least two chips in the side by side proximal arrangement. The at least two chips include a plurality of electric connections that are directly coupled to corresponding electrical connections on the bridge and on the packaging substrate.

Direct bonded heterogeneous integration packaging structures

Spacer for die-to-die communication in an integrated circuit

A multiple chip carrier assembly including a carrier having a first surface and a second surface is attached to a plurality of chips is described. The plurality of chips include a first chip and a second chip. Each of the chips has first surface with a first set of solder balls for connecting to a package and a second set of solder balls for connecting to a high signal density bridge element. A second surface of each chip is bonded to the first surface of the carrier. A package has a first surface which is connected to the first sets of solder balls of the first and second chips. A high signal density bridge element having high signal density wiring on one or more layers is connected to the second sets of solder balls of the first and second chips. The bridge element is disposed between the first surface of the package and the first surfaces of the first and second chips.

Multiple chip carrier for bridge assembly

An integrated circuit (IC) chip carrier includes one or more memory devices therein. The memory is integrated into the carrier prior to the IC chip being connected to the carrier. Therefore, the IC chip may be connected to the memory at the same time as the IC chip is connected to the carrier. Because the memory is integrated into the IC chip carrier, prior to the IC chip being attached thereto, reliability concerns that result from attaching the memory to the IC chip carrier affect the IC chip carrier and do not affect the yield of the relatively more expensive IC chip.

Carrier and integrated memory

An integrated circuit (IC) chip carrier includes one or more memory devices therein. The memory is integrated into the carrier prior to the IC chip being connected to the carrier. Therefore, the IC chip may be connected to the memory at the same time as the IC chip is connected to the carrier. An access instruction may be sent from the IC chip to the memory through a wiring line of the IC chip carrier. Power potential may be sent from a system board to the memory through a vertical interconnect access (VIA). Alternatively, an access instruction may be sent from a first IC chip to the memory and power potential may be sent from a second IC chip to the memory.

A technique relates to forming a chip assembly. Top and bottom chip stack elements containing solder pads and a solder material are provided. Soluble standoffs are applied to the bottom chip stack element. The chip stack elements are aligned to bring the top solder pad in proximity to the bottom solder pad and the temperature is raised to a temperature above the melting temperature of the solder material to form a connected chip assembly. The connected chip assembly is cooled to re-solidify the solder material and soluble standoffs are removed from the connected chip assembly.

Selectively soluble standoffs for chip joining

A frontside of a chip is bonded to a top surface of a chip carrier. Seal material is dispensed at a periphery of the top surface of the chip carrier. A solder TIM having a first side and a second side is provided. The first side of the TIM contacts a backside of the chip. A reflow is performed to melt the TIM. The second side of the TIM is bonded to a lid. The seal material is cured. The lid is attached to the top surface of the chip carrier. Backfill material is injected into a space between the top surface of the chip carrier and the lid. The backfill material abuts sides of the TIM. The backfill material is cured. TIM solder cracking and associated thermal degradation are mitigated.

Reliability enhancement of metal thermal interface

A method and structure is disclosed for detaching a chip from a substrate that delays the delivery of shear force to the chip until the connectors attaching the chip to the substrate are soft enough that the delivery of shear force will not damage the chip's connectors. More particularly, the shear force is created by a bimetallic disk that, when heat is applied, is transformed into shearing force. The shearing force is delayed by a delaying device until the connectors connecting the chip to the substrate are soft enough that the application of shear force will separate the chip from the substrate without damaging the chip's connectors. The delaying device includes a physical gap that may be adjusted to control when the shear force is applied to the chip.

Method and apparatus for removing known good die

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Fishkill, NY, United States of America

Mark William Kapfhammer