Pmc-sierra, Inc.

Alcatel Canada Inc.

Alcatel-lucent Canada Inc.

Mark William Janoska

Henry Chow

Hossain Pezeshki-Esfahani

Albert D Heller

Srinivasan Ramaswamy

Anthony Hung

Jason Chen

A method and apparatus for line card redundancy in a communication switch is presented. The switch includes an arbiter coupled to the input of a switch core and a line card pair. The first line card of the line card pair is considered an active line card, whereas the second line card of the line card pair is considered the redundant, or inactive, line card. The active and inactive line cards are determined based on selection information received by the arbiter. Based on the selection information, the arbiter preferentially provides ingress data from the active line card to the corresponding input of the switch core. A router is coupled to the line card pair and to an output of the switch core. The router passes egress data from the switch core to at least one of the first and second line cards based on routing information included in the egress data.

Method and apparatus for line card redundancy in a communication switch

Methods and devices for scheduling data transmission processing based on the size of the data transmission unit and a predetermined increment value. A scheduler has slots which represent specific amounts of time in which a queue of data transmission units to be processed is represented. An indicator determines which slot and thereby which queue is being examined. Each queue is assigned a specific increment value and each data transmission unit in a queue is assigned a count value based on the size of the data transmission unit. When a data transmission unit is at the head of the queue and is a candidate for processing, if the count value is greater than a predetermined value then the queue and thereby the data transmission unit at the head of the queue is rescheduled at a later time. This is effected by assigning the queue to a subsequent slot in the scheduler. The subsequent slot in the scheduler is determined based on the given increment value for that queue. The increment value is based on how many data transmission units are desired to be processed within a given amount of time.

Packet shaping on a fixed segment scheduler

A data traffic management system that has the capability of writing data to the buffer memory at twice its normal rate. The data traffic management system uses a pointer structure that can reference either a single or a dual segment memory bank. A dual segment memory bank enhances the write capability of the data traffic management system by allowing two segments to be simultaneously written to both segment memory banks, with one segment being written to each bank. A pointer data structure with a single/dual indicator (S/D indicator) is used for referencing the memory banks. If the S/D indicator has a D entry, then a dual segment memory bank is addressed. The S/D indicator will have an S entry if a single segment memory bank is addressed. Based on the contents of the S/D indicator, either a single fixed size data segment is written to a single memory bank or two fixed size data segments are written to a dual segment memory bank.

Transporting data transmission units of different sizes using segments of fixed sizes

Methods and devices for arranging memory access operations to minimize memory bank conflicts between such operations. A fixed pattern of memory access operations is implemented to minimize the effects of a transition between a read memory access operation and a write memory access operation. A write-read-gap (WRG) set pattern of a write memory access operation followed by a read memory access operation and then followed by a set gap when no memory access operation may be undertaken, meets the particular requirements of RDRAM. Within the WRG pattern, read addresses and write addresses are selected to minimize memory bank access conflicts. Such selections are assisted in increasing the efficiency of the memory access operations by defining a set frame size of a specific number of repetitions of the WRG pattern. All memory access operations are then rearranged to conform to the WRG pattern and, the repetitions of the WRG pattern are divided into frames having a size equal to that of the defined frame size. Within each frame, the read addresses to be accessed by read memory operations can be rearranged to minimize memory bank access conflicts with either write addresses to be accessed by write memory operations or other read addresses.

Method of allowing random access to rambus DRAM for short burst of data

A method and apparatus is for buffering data cells in a queuing element is presented. Each queuing element includes a partitioned buffer, where the partitioned buffer includes a plurality of partitions. Each of the partitions stores data cells received by the queuing element. Storage of the data cells into the partitions is accomplished by using an array of logical queues. Each logical queue of the array of logical queues maps data cells corresponding to that logical queue to a particular partition of the plurality of partitions. More than one logical queue may map data cells to a particular partition. Each partition may include a reserved portion, where each logical queue that maps to the partition may map a portion of its data cells to the reserved portion. The resources of the reserved portion to which a logical queue maps data cells are reserved to that specific logical queue and cannot be utilized by other logical queues. Each partition also includes a shared portion, where all of the logical queues that map to a partition are able to utilize the storage space included in the shared portion. Each logical queue includes a maximum size. Depth pointers corresponding to the logical queue and the partition are updated as data cells are enqueued to, and dequeued from, the logical queue.

Method and apparatus for data buffer management in a communications switch

A method and apparatus for a high bandwidth multi-source interconnection using point-to-point buses that may be utilized in a communication switch is presented. In the communication switch, a number of output buffers are included to correspond to the outputs of the switch. Each output receives data from a number of different inputs to the switch. Each output buffer includes a plurality of queuing elements where each queuing element receives data from at least one of the inputs and buffers the data prior to insertion into an output data stream corresponding to the output of the output buffer. The plurality of queuing of elements are intercoupled in a daisy chain configuration such that a daisy chain output of one queuing element is coupled to the daisy chain input of the succeeding queuing element. The daisy chain configuration provides a data path through which a data stream that becomes the output of the output buffer is carried. A chain master queuing element at the head of the daisy chain inserts idles into the data stream unless an arbiter has instructed it to insert data that it has received from its corresponding inputs. Succeeding queuing elements on the daisy chain then receive the data stream and insert their data at the appropriate time determined by the arbitration grants received from the arbiter.

Method and apparatus for high bandwidth multi-source interconnection using point-to-point buses

The method for servicing queues holding messages, such as ATM data packets, for subsequent processing or transmission to a resource such as a communications link having a finite processing capability comprises the steps of servicing each queue by forwarding the messages thereof to the resource at time intervals corresponding to a guaranteed service rate of the queue, provided the queue is non-empty; and, during time intervals when none of the queues have messages being forwarded to the resource in conformance with the above step, servicing the queues in accordance with a proportion of a remaining or idle resource bandwidth allocated to each queue. The method is preferably carried out by a hierarchical scheduler comprising an exhaustive sub-scheduler servicing a plurality of lower level sub-schedulers in accordance with non-equal priority levels assigned thereto; M non-work conserving shaper sub-schedulers feeding the exhaustive sub-scheduler; and N work conserving idle bandwidth sub-schedulers feeding the exhaustive sub-scheduler. In such a scheduler, a queue concurrently contends for service by one of the shaper sub-schedulers and one of the idle bandwidth sub-schedulers, wherein the shaper sub-scheduler servicing the queue has a higher priority level with respect to the exhaustive sub-scheduler than the idle bandwidth sub-scheduler servicing the same queue. The technique distributes the idle bandwidth of the resource in a way which is de-coupled from the guaranteed service rates of the queues, thereby providing a more efficient bandwidth distribution.

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Mark William Janoska