Intersil Americas Inc.

Intersil Corporation

Mark William Dickmann

James William Leith

In a phase-locked loop (PLL), a phase detector receives a reference signal and a feedback oscillator signal, generates a phase-detect pulse having a first duration in response to one of the reference and feedback signals, and generates a phase-correction pulse having second, shorter duration in response to the phase-detect pulse. By shortening the phase-correction pulse, such a phase detector can reduce or eliminate the overcorrection period during which the phase-correction pulse is active after phase correction is achieved, and thus can reduce or eliminate the phase error that the overcorrection period may introduce into a PLL's oscillator signal.

Phase detector and method for a shortening phase-error-correction pulse

A pulse-width modulation (PWM) controller to supply power to electronic components using a phase lock loop (PLL) is presented. A PWM controller comprises an input node operable to receive a reference signal and a phase-locked loop (PLL). The PLL comprises an oscillator operable to receive an error-correction signal and to generate an oscillator signal having a frequency that is related to the error-correction signal, a phase-frequency detector (PFD) coupled to the oscillator and operable to receive the reference signal and to generate the error-correction signal based upon a phase difference between the reference signal and a feedback signal, and a suppression circuit coupled to the PFD and operable to periodically enable the PFD to generate the error-correction signal.

PWM controller with integrated PLL

A phase-locked loop having a programmable loop bandwidth is provided. A PLL comprises an oscillator operable to receive an error-correction signal and to generate an oscillator signal having a frequency that is related to the error-correction signal. The PLL further comprises a phase-frequency detector (PFD) coupled to the oscillator and operable to receive a reference signal and to generate the error-correction signal based upon a phase difference between the reference signal and a feedback signal derived from the oscillator signal. The PLL further comprises an error-correction signal suppression circuit coupled to the PFD and operable to control the loop bandwidth of the PLL by periodically enabling the PFD.

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Bellevue, WA, United States of America

Mark William Dickmann