Altera Corporation

Mark Webb

Chee Wai Yap

Joseph DeLaere

A PLD having real-time in-system programmability (ISP) capability is provided. The PLD includes a configuration memory region into which the updated configuration is obtained. A user memory region stores the state for registers of the PLD. The configuration memory region communicates the updated configuration to a core logic region that includes a real-time ISP detection block that detects the initiation of a real-time ISP operation. A controller is in communication with the logic block. The PLD maintains register data by reading a state of the registers of the PLD/logic block and clamping the output pins before the core logic region is being updated. The state of the registers is saved in the memory region as directed by the controller. Upon completion of the update into the logic array, the registers of the PLD are cleared and a control signal from a memory interface triggers the controller to read stored the register data back from the memory and reload the registers. Upon the completion of reloading the registers, the output pins are released for normal device operation.

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Austin, TX, United States of America

Mark Webb