International Business Machines Corporation

Huntsman International LLC

Mark Wayne Mueller

Peter Matthew Thomsen

Lucinda Mae Walter

Daniel Ernest Hurlimann

Lee Hardy Wilson

Girish Chandra Johari

Vinh B Lu

Thomas S Parker

Kirby L Watson

John R Sanderson

John Saunders Corbin, Jr

Sudhir Dhawan

Kenneth Carl Larsen

Douglas Marvin Benignus

Gary T Hunt

Silous F Clements

Wallace G Tuten

James M McVey

Ernest L Miller

Kevin Lynn Hill

David Allen Hall

James L Frye

Ronald Smetana

James P Farone

A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design for addressing deficiencies of the art in respect to hypertransport-based switching for multi-CPU systems and for flexibly configurable multi-CPU supported hypertransport switching is provided. The design structure can include a hypertransport switching data processing system. The system can include a CPU and at least two I/O bridges. Each I/O bridge can provide a communications path for data driven to a corresponding peripheral device from the CPU. Notably, the system can include a flexibly configurable hypertransport switch. The switch can include a first configuration adapting the CPU to both of the I/O bridges, and a second configuration adapting the CPU to a first one of the I/O bridges and a second CPU to a second one of the I/O bridges.

Structure for a flexibly configurable multi central processing unit (CPU) supported hypertransport switching

Embodiments of the invention address deficiencies of the art in respect to hypertransport-based switching for multi-CPU systems and provide a method, system and computer program product for flexibly configurable multi-CPU supported hypertransport switching. In one embodiment of the invention, a hypertransport switching data processing system can be provided. The system can include a CPU and at least two I/O bridges. Each I/O bridge can provide a communications path for data driven to a corresponding peripheral device from the CPU. Notably, the system can include a flexibly configurable hypertransport switch. The switch can include a first configuration adapting the CPU to both of the I/O bridges, and a second configuration adapting the CPU to a first one of the I/O bridges and a second CPU to a second one of the I/O bridges.

Flexibly configurable multi central processing unit (CPU) supported hypertransport switching

This invention concerns a process for removing carbonyl-containing impurities from impure extractive distillation solvent such as a glycol, comprising: contacting the impure extractive distillation solvent with an acidic ion exchange resin. The purified extractive distillation solvent can be recycled for use as a solvent in an extractive distillation process that removes impurities from alkylene oxide. The extractive distillation solvent can be ethylene glycol monomethyl ether (EGME) used to purify propylene oxide.

Purification of solvents used for the purification of alkylene oxide

A method of servicing a computer system without interrupting operation of the computer system, by connecting a computer component to a board of the computer system, detecting connection of the computer component to the system board using a control circuit, supplying power to the voltage input of the computer component in response to detecting the connection, and thereafter monitoring the power supplied to the voltage input of the computer component. The method may be used for core computer components such as CPU modules and voltage regulator modules. Power to the voltage input of the computer component is turned off in response to a determination that a current level of the power supplied to the voltage input exceeds a specified level. A fault signal is latched in an active state in response to the determination; the fault signal is reset when the component is removed from the system. The method also applies to a plurality of hot-pluggable components, wherein the power supplied to each component is individually monitored.

Hot plug control of MP based computer system

A method and system for monitoring and adapting to configuration changes in a data processing system having a known configuration, while power is applied thereto. In response to a configuration change in the data processing system, values are calculated for multiple system operating factors. An alert is provided to a user if at least one of said calculated values, among the multiple system operating factors, is not within a predetermined range of values for the multiple system operating factors. In addition, the operation of the data processing system is restricted to accommodate for any system operating factors which are not within the predetermined range of values, such that the data processing system is guarded from damage due to an unstable configuration.

Method and system for monitoring configuration changes in a data processing system

A power subsystem for a computer system allows a voltage regulator module (VRM) to be removably connected to a system board, while limiting disturbances on the voltage rails of the system board. The electrical disturbances are prevented by charging voltage outputs of the DC/DC circuit of the VRM prior to directly connecting the voltage outputs to the voltage rails. To ensure that the voltage outputs are properly charged, a VRM connector may be used in which the voltage output pins are shorter than charge pins which are coupled to respective capacitors and to the voltage outputs of the DC/DC circuit. In this manner, as the connector is mated with a corresponding connector on the system board, the capacitors are first charged via resistive paths connected to the voltage rails, prior to directly connecting the voltage outputs to the voltage rails. The VRMs are thus &ldquo;hot-pluggable,&rdquo; enabling a user to upgrade or service the system with no interruption.

Hot-pluggable voltage regulator module

A circuit card capable of live insertion into an activated electronic system includes a terminal edge from which an edge connector extends a first length. An input decoupling capacitance resides across the edge connector. A backplane within the activated electronic system receives the circuit card, wherein the backplane includes at least one voltage plane, a backplane receptor, and card guide receptor means. The backplane receptor electrically couples the edge connector to the voltage plane when the edge connector engages the backplane receptor. Card guide means are provided for guiding and connecting the circuit card into the backplane, and include at least one conductive member for engaging the card guide receptor means. The conductive member extends a second length from the terminal edge, wherein the second length is greater than the first length. At least one conductive path electrically couples the conductive member across the input capacitance. A voltage supply applied to the card guide receptor means ensures that during insertion of the circuit card into the backplane, but prior to the backplane receptor engaging the edge connector, the input capacitance will pre-charge through the conductive member, thereby preventing arcing and voltage dropout.

Pre-charging logic cards for hot insertion

A device for solving the electrical, physical, architectural and thermal challenges associated with designing a computer system is disclosed. A memory controller chipset having two or more chips mounted on opposite sides of a system planar helps balance the thermal profile of the system and achieve the strict spacing requirements of advanced computer processors relative to the memory controller chipset. Although the chips are staggered on opposite sides of the system planar, the adjacent edges of the chips substantially align with one another to minimize their separation.

Computer system utilizing front and backside mounted memory controller chipsets

A mechanism has a subassembly that contains a microprocessor. The mechanism allows the microprocessor to be easily installed through frontal or rear access into a rack drawer and subsequently docked into a receiving assembly. The docking mechanism is multi-axis in that installation of the subassembly occurs along a single axis, but docking of the microprocessor occurs along an axis that is normal to the installation axis. Actuation of the installation mechanism is accomplished with a front-to-rear motion which sequentially provides a power connection to the microprocessor and displaces it in a vertical motion. This vertical motion registers and mates the microprocessor with the assembly. The microprocessor is preloaded in its final latched position to restrain it from shock and vibration events while supporting the assembly in a fixed and stable position.

Multi-axis microprocess or docking mechanism

A system for dissipating electrostatic build-up from a circuit card to a chassis ground within an electronic system, prior to connection of the circuit card with the electronic system. A circuit card has a card connector for connecting the circuit card into a backplane receptor within the electronic system. The circuit card includes a surface upon which an electrostatic charge may collect and also includes at least one conductive pad. A card guide aligns the circuit card such that the circuit card connects with the backplane receptor when said circuit card is fully inserted into the card guide. A conductive element within the card guide couples the conductive pad to a chassis ground within the electronic system when the circuit card is partially inserted into said the card guide.

Discharging electrostatic charge during hot card insertion

The present invention describes an integrated text and data processing system allowing processing of link data before output. The system also provides simultaneous dual emulation of a display and printer normally associated with a host data processor. In accordance with the first aspect of the invention, an input/output terminal includes a support logic circuit for interconnecting the input/output terminal to a port of an intermediate control unit attached to a central processing unit. The input/output terminal includes separate link and display buffers whereas link data may be stored in the link buffer for processing before output to the display associated with a text processor. In accordance with another aspect of the invention, the input/output terminal may include a plurality of support logic circuits each connected to one of the ports of one or more control units associated with one or more central processing units. This structure allows the text processor in the input/output terminal to simultaneously yet independently emulate a display and printer normally associated with a host central processing unit.

Integrated data processing/text processing system having a terminal with

A communication adapter circuit (10) is connected to a processor through a data bus (12)and a control bus (14). Data and control signals are provided through the buses (12,14) to a timer circuit (18), a programmable peripheral interface circuit (20), an asynchronous and bisynchronous control circuit (22) and an SDLC/HDLC control circuit (24). Each of the control circuits (22, 24) includes parallel-to-serial and serial-to-parallel conversion circuitry. A clock select circuit (32) operates in conjunction with the timer circuit (18) and the programmable peripheral interface circuit (20) to establish a data transmission rate for the data flow through the adapter circuit (10). From the control circuits (22, 24) the data is transmitted through a bi-directional serial line (44) to a dual modem switch (56). From the switch (56) the data is transmitted to either an EIA interface circuit (60) to a conventional modem or through a line (64) to an internal modem.

Communication adapter circuit

A communication adapter circuit (10) is connected to a processor through processor I/O interface buses (12, 14). Data and control signals are provided through the buses (12, 14) to a timer circuit (18), a programmable peripheral interface circuit (20), an asynchronous and bisynchronous control circuit (22) and an SDLC/HDLC control circuit (24). Each of the control circuits (22, 24) includes parallel-to-serial and serial-to-parallel conversion circuitry. A clock select circuit (32) operates in conjunction with the timer circuit (18) and the programmable peripheral interface circuit (20) to establish a data transmission rate for the data flow through the adapter circuit (10). From the control circuits (22, 24) the data is transmitted through a modem interface bus (44) to a dual modem switch (56). From the switch (56) the data is transmitted to either an EIA RS 232 interface circuit (60) to a conventional modem or through a bus (64) to an internal modem. A phase locked loop (PLL) circuit in the control circuit (24) generates a data clock signal on a line (33) for operation of the adapter circuit (10) in the bisynchronous protocol with a non-clock-generating modem.

Growing community of inventors

Austin, TX, United States of America

Mark Wayne Mueller