Stmicroelectronics (rousset) Sas

St-ericsson Sa

Stmicroelectronics (grenoble 2) Sas

Ericsson Modems Sa

Telefonaktiebolaget Lm Ericsson (publ)

Mark Wallis

Jean-Francois Link

Joran Pantel

Pierre Demaj

Yoann Bouvet

Issam Toufik

Laurent Lestringand

Yannick Sebillet

Eric Alliot

In accordance with an embodiment, a system-on-chip includes: a memory circuit comprising a first memory region accessible with a first access right level and a second memory region accessible with the first access right level or a second access right level, at least one first peripheral having the first access right level, at least one second peripheral having the second access right level; and a direct memory access circuit configured to generate direct memory accesses, wherein the direct memory access circuit includes at least one first direct memory access controller having the first access right level and at least one second direct memory access controller having the second access right level.

System-on-chip incorporating a direct memory access circuit and corresponding method

An integrated circuit includes a programmable logic block. The programmable logic block includes a programmable logic array (PLA) and a field programmable gate array (FPGA). The PLA includes logic cells having a first architecture. The FPGA includes logic cells having a second architecture more complex than the first architecture. The programmable logic block includes an interface coupled to the PLA and the FPGA. An integrated circuit may also include circuitry for selecting one of plurality of clock signals for logic cells of a PLA.

Programmable logic block with multiple types of programmable arrays and flexible clock selection

A system on chip includes a programmable logic array. The system on chip also includes a signal conditioner coupled to a data input of the programmable logic array and configured to condition a data signal prior to processing the data signal with the programmable logic array. The signal conditioner can selectively condition the signal by one or both of synchronizing the data signal with a clock signal of the programmable logic array and generating a pulse from the data signal with an edge detector.

Input signal shaping for a programmable logic array

An integrated circuit includes a programmable logic array. The programmable logic array incudes a plurality of logic elements arranged in rows and columns. Each logic element includes a direct output and a synchronized output. The direct output of each logic element is coupled to all other logic elements of higher rank, but is not coupled to logic elements of lower rank.

Programmable logic array with reliable timing

A microcontroller is capable of executing a process that is parameterizable by at least one parameter. The microcontroller includes a processor and a hardware module coupled to the processor. The hardware module is configured to hardware execute the process and the processor is configured to deliver the at least one parameter to the hardware module.

Microcontroller for executing a configurable processing operation

A method is for processing an analog signal coming from a transmission channel. The analog signal may include a useful signal modulated on a sub-set of carriers. The method may include analog-to-digital converting of the analog signal into a digital signal, and synchronization processing the digital signal. The synchronizing may include determining, in a time domain, a limited number of coefficients of a predictive filter from an autoregressive model of the digital signal, and filtering the digital signal in the time domain by a digital finite impulse response filter with coefficients based upon the limited number of coefficients to provide a filtered digital signal. The method may include detecting of an indication allowing a location in the frame structure to be identified, using the filtered digital signal and a reference signal.

Method for processing an analog signal coming from a transmission channel, in particular a signal carried by power line communications

A method includes digital/analog conversion of a digital signal modulated by information to provide a modulated initial analog signal having a crest factor greater than one, and amplification of the initial analog signal to provide an amplified modulated signal. A modulated channel analog signal derived from the modulated amplified analog signal is transmitted over a communications channel, with impedance of the communications channel varying during the transmission. The method further includes at least one determination during the transmission of a peak-clipping rate of the amplified analog signal over at least one time interval, and an adjustment of a level of the initial analog signal as a function of the determined peak-clipping rate.

Method and device for transmitting information over a communication channel with variable impedance

A process for computing cubic metric used for performing Maximum Power Reduction (MPR) in the transmitter of a User Equipment communicating with a base station (BS), said cubic metric computation being performed before each time slot of said uplink transmission of data; said process being characterized in that it involves the steps of: &#x2014;using PN generators (-) for generating random data which are used for performing said cubic metric computation, and &#x2014;using the result of said computation for applying said Maximum Power Reduction (MPR) for each time slot of said uplink transmission.

Process for performing cubic metric computation in the transmitter of a UE for a wireless communication system, and apparatus for performing the same

Method for identifying within an incident signal at least one frequency communication channel, the incident signal being received on a wireless apparatus, comprising determining a power spectral density (PSD) of that incident signal and identifying the at least one channel from the PSD. The PSD determination comprises storing temporal samples of the incident signal received during a predetermined duration and performing a first Discrete Fourier Transform (DFT) processing on the stored samples.

Method and device for identifying at least one communication channel with an incident signal

This method of reading a plurality of chip sample values at tap positions () in a digital delay line () having a starting point and an end point for delaying symbols of a signal () received in a receiver comprises:&#x2014;reading the plurality of chip sample values in the digital delay line () at the tap positions () according to a chip rate clock () having a chip rate clock cycle and a chip rate clock frequency,&#x2014;oversampling the received signal () according to a sample rate clock () having a sample rate clock cycle and a sample rate clock frequency to produce a plurality of chip sample values supplied in the digital delay line (), the sample rate clock frequency being higher than the chip rate clock frequency,&#x2014;shifting the tap positions () towards either the starting point or the end point of the digital delay line (), and&#x2014;adjusting the chip rate clock cycle when shifting the tap positions.

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Mouans Sartoux, France

Mark Wallis