Compaq Computer Corporation, Inc.

Duke University

Mark W Welker

Thomas M Albers

John V Eberst

Richard L Pyra

Jack E Bresenham

Darwin Fontenot

Paul B Wood

John S Thayer

David W Engler

Thomas J Bonola

Michael P Moriarty

Gary J Piccirillo

Richard M Knox

Wood, Paul B

A monitor provides analog conditioning circuitry for supplying a symmetrical high speed analog output signal generated from inverted and non-inverted digital data to imagers for a display of the monitor. The circuitry includes an upper bias amplifier for generating a precision upper DC offset signal. a lower bias amplifier for generating a precision lower DC offset signal, a switch for alternating selection of a precision DC offset signal with each frame, and a summing amplifier for adding the selected precision DC offset signal to a high speed analog signal provided by a digital-to-analog converter. Selection of the precision DC offset signal is controlled by an inversion signal provided to the switch from an inversion bit of a display controller. The digital data inversion is controlled by inversion circuitry within the display controller. The analog conditioning circuitry thus provides a single gain path and also provides low speed signal paths decoupled from a high speed signal path.

Analog conditioning circuitry for imagers for a display

Monitors for use in a tiled monitor system include adjacent monitor detectors arranged to detect the presence of corresponding adjacent monitor detectors on adjacent monitors so that the physical arrangements of the tiled monitors can be determined without user intervention. Similarly, orientation sensors are provided in each monitor so that their orientation&mdash;landscape vs. portrait&mdash;can be determined by the monitor without user intervention and reported to the video controller.

Video display configuration detector

A graphics processor uses a line draw facility to receive first and second values indicative of the coordinates of respective first and second end points of a line. The reception of the second value is sensed by the line draw facility and line data is generated responsive to the sensing of the second value.

Video graphics controller with high speed line draw processor

A tiled monitor system is implemented with a single controller that does not provide standard video signals to each of the monitors. Instead, only the changed portions of an image to be displayed are sent to the monitors, which internally maintain a video frame buffer for displaying using a display engine. Preferably, a high speed serial link is used between the monitors and the video controller for transmitting this information.

Multi-tile video display system with distributed CRTC

A method and apparatus of allocating memory space in a main memory of a computer system to a unified memory architecture device. The main memory is associated with a physical address space. A required linear address range is determined for the video card, and the linear address range is mapped to scattered portions in the physical address space. A page table is created containing page frame numbers corresponding to page frames in the main memory, the page frames being allocated to the device. The page frames are non-contiguous blocks of the main memory. The device is associated with a linear address space. The frame numbers are loaded into a translation look-aside buffer (TLB) for converting a linear address in the linear address space to a physical address in the physical address space.

Method and system for allocating memory space using mapping controller, page table and frame numbers

A monitor provides analog conditioning circuitry for supplying a symmetrical high speed analog output signal generated from inverted and non-inverted digital data to imagers for a display of the monitor. The circuitry includes an upper bias amplifier for generating a precision upper DC offset signal, a lower bias amplifier for generating a precision lower DC offset signal, a switch for alternating selection of a precision DC offset signal with each frame, and a summing amplifier for adding the selected precision DC offset signal to a high speed analog signal provided by a digital-to-analog converter. Selection of the precision DC offset signal is controlled by an inversion signal provided to the switch from an inversion bit of a display controller. The digital data inversion is controlled by inversion circuitry within the display controller. The analog conditioning circuitry thus provides a single gain path and also provides low speed signal paths decoupled from a high speed signal path.

A computer system providing multiple processors or masters an architecture for highly concurrent processing and data throughput. A multiple channel memory architecture provides concurrent access to memory. Arbitration and snoop logic controls access to each memory channel and maintains cache coherency. A host CPU, multimedia processor, pipes processor and display controller may independently and concurrently access memory. The pipes processor provides a decoupled input/output processor for universal serial bus and firewire serial buses to free up the host CPU.

Multimedia computer architecture with multi-channel concurrent memory

A graphics device includes first and second endpoint memories where coordinates of a line can be stored. State logic within the graphics device calculates line parameters from the first and second endpoints. The calculated line parameters include a line error term which can be stored in an error term memory. The error term memory is writeable from a source external to the graphics device, such as the CPU of a computer system, so that the external source can modify the contents of the error term register.

Video graphics controller with improved calculation capabilities

A method and apparatus of assuring uniqueness of identification numbers of bus devices connected to a bus. Each bus device has a current identification number. At each of the bus devices, an identification number is received on a bus and the bus is contended for based on the received identification number. If more than one bus device is detected contending for the bus, the current identification number of one of the bus devices is changed. Each of the bus devices compares the received identification number to the current identification number of the bus device. A bus device provides a match indication, including driving a signal, if the comparison produces a match. Each bus device includes a collision detector for detecting if more than one bus device is driving the signal.

Avoiding non-unique identifiers for bus devices

A computer system which includes a DMA controller on the local I/O unit which can be programmed by either the host processor or the local processor. Semaphore flags and lock bits are provided to allow determination of control of the local DMA controller and for passing information. Additionally, data alignment and padding circuitry is provided. The circuitry is informed of the logical data arrangement desired or utilized by the host processor or other devices and knows the data arrangement of the local processor. The circuitry properly obtains and realigns the data based on the transfer direction and data arrangement. The circuitry further properly zero pads the data when realignment is such that padding is necessary.

DMA controller which can be controlled by host and local processors

Video graphics controller with automatic starting for line draws

Line draw circuitry receives parameters defining first and second endpoints of a line and calculates line parameters based on the first and second endpoints. The line parameters are then stored in a memory. A 'calculate-only' control signals determines whether a line is drawn immediately after calculation (and storing) of the end parameters or whether the line is drawn responsive to a subsequent 'start' signal. If the line is to be drawn responsive to the start signal, the line parameters may be modified prior to drawing the line.

System fpr transferring data between two buses using control registers

A circuit for configuring a Plug and Play expansion card in one of three ways. The first is the standard Plug and Play configuration method, wherein expansion cards go through the isolation process to obtain unique Card Select Numbers (CSN). This method requires the existence of a dedicated serial EEPROM to store the system resource data for the expansion cards. However, when an expansion card is directly mounted onto a system board, it becomes a system board device. This allows the separate serial EEPROM to be removed. To implement, two alternative configuration modes are provided, wherein the expansion card can be configured under main CPU control. In these alternative modes, the configuration data is stored in the main system BIOS ROM. In the first mode, a register in the expansion card is mapped to a fixed ISA I/O address. In the second mode, the register is controlled by a dedicated pin, thus allowing it to be mapped to any ISA I/O address. To determine which configuration mode is used by the expansion card, pullup or pulldown resistors are connected to certain expansion card output pins. A second embodiment is also described wherein a static random access memory (SRAM) is utilized to store the serial identifier and the resource data. In this embodiment, the system BIOS initially writes the serial identifier and resource data into the SRAM. After this is done, a Plug and Play configuration process is invoked, in which the serial identifier is retrieved from the SRAM rather than the serial EEPROM.

Expansion device configuration system having two configuration modes

Circuitry for drawing lines includes a video memory for storing pixel data and circuitry for generating a sequence of addresses defining a line of pixels in the video memory. A first memory stores a sequence of pattern units corresponding to the generated sequence of addresses. A second memory stores a value indicating a current pattern unit. Writing circuitry writes to the video memory at a generated address responsive to a current pattern unit. A third memory stores a control value which is accessed by update circuitry for updating the second memory to indicate the next pattern unit. The update circuitry may selectively update the second memory to the sequential pattern unit or reset the second memory to a predetermined pattern unit.

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Spring, TX, United States of America

Mark W Welker