Harris Corporation

Mark W Thompson

Brian Padalino

Jeffrey A Kroon

Donald R Martz

George D Helm

Robert E Daminski

Brian C Padalino

A transmitter includes an input, a modulator, and a calibration memory configured to store discrete calibration test points. A compensator is coupled between the input and the modulator and cooperates with the calibration memory to cause the modulator to generate a respective calibration carrier signal for each of the discrete calibration test points during a calibration phase. A detector is coupled to an output of the modulator and is configured to determine respective calibration values of the calibration carrier signals during the calibration phase. A compensator calculator is coupled to an output of the detector, and is configured to generate compensation values for the compensator for use during an operation phase and based on the calibration values of the calibration carrier signals.

Transmitter including calibration of an in-phase/quadrature (I/Q) modulator and associated methods

A system adapts power for minimizing the total amount of transmitted power in a wireless communications network. A transmit station transmits a communications signal requesting a response from receiving mobile stations. A plurality of the mobile stations receives the communications signal and each evaluates the signal reception, such as the signal-to-noise ratio or transmitted power. Each mobile station responds by transmitting a communications signal back to the transmit station in a specific time slot as a function of the signal reception to allow the transmit station to adapt its power based on the time slot of the communications signals received from respective mobile stations. This minimizes the total amount of power transmitted by the wireless communications network.

System that adapts power for minimizing the total amount of transmitted power within a wireless communications network and related method

A system of downconverting an intermediate frequency (IF) phase or frequency modulated signal to a digital baseband includes an N bit shift register circuit that receives a binary input as a 1-bit input sample data stream of an IF signal. A decimation circuit includes a memory and receives data from the N bit shift register circuit and stores N 1-bit binary samples as address bits and performs decimation, downconversion and filtering by accessing memory values at a predetermined rate.

Decimating down converter and related methods

A bi-directional amplifier having two symmetrical and versatile impedance matching circuits with a JFET therebetween, and a method for bi-directional amplification using a JFET. Each junction of the JFET may be a drain or a source depending on the direction of amplification. Each impedance matching circuit provides a low impedance for the junction that is a source and a high impedance for the junction that is a drain. The impedance is varied by adding a first capacitor parallel to a resonating inductor and a second capacitor, which is removed or inserted in series with the load, responsive to the direction of amplification. The frequency of the signal being amplified may be different for each direction.

Growing community of inventors

Fairport, NY, United States of America

Mark W Thompson