Cypress Semiconductor Corporation

Parade Technologies, Ltd.

Mark W Rouse

Eric D Blom

Harold Kutz

Warren S Snyder

Andrew J Walker

Patrick N Prendergast

Brenor L Brophy

Kenelm G Murray

John Roy

Ba Kang Chu

Xuan Nguyen

A capacitive sense array configured to improve noise immunity in detecting a presence of a conductive object is described. In one embodiment, a capacitive sense array includes at least a first set of sense elements disposed in straight parallel lines along a first axis of the capacitive sense array. A second set of sense elements is disposed in crooked paths about a second axis of the capacitive sense array. The first and second sets form a capacitive sense array that includes crooked sense paths in at least one of the axes of the sense array.

Sensor patterns with reduced noise coupling

A variable reference voltage circuit for performing memory operation on non-volatile memory includes a multi-level voltage source and a selector circuit. The multi-level voltage source generates multiple voltages. The selector circuit includes a selector input and a selector output. The selector input is coupled to the multi-level voltage source to selectively couple any of the multiple voltages to the selector output. The selector output of the selector circuit is coupled to a non-volatile memory array to provide the NV memory array with a selectable program voltage for programming the NV memory array and a selectable erase voltage for erasing the NV memory array.

Variable reference voltage circuit for non-volatile memory

A method and apparatus for verifying non-volatile memory. A first transmission of data is received by a first memory of a device. The data is received by a non-volatile memory of the device. The data received by the non-volatile memory is verified by comparing it to the data in the first memory with comparison logic of the device. The verification is performed without receiving a second transmission of the data and without sending a second transmission of the data. A result is generated from the comparison.

Self verification of non-volatile memory

A method for programming a memory device is disclosed. In one method embodiment, the present invention receives a measurement from a temperature sensor located near a non-volatile programmable memory device. Next, a transformation is accessed. Then, the measurement from the temperature sensor is processed in conjunction with the transformation to establish a programming time for a memory device as a function of a programming voltage and the temperature of the memory device. The programming voltage is then applied to the memory device for the length of time specified by the programming time during the programming pulse of the memory device to accurately program the device using an optimum amount of current.

Method and system for programming a memory device

A semiconductor device includes a grounded-gate n-channel field effect transistor (FET) between an I/O pad and ground (V ) and/or V for providing ESD protection. The FET includes a tap region of grounded p-type semiconductor material in the vicinity of the n -type source region of the FET, which is also tied to ground, to make the ESD protection device less sensitive to substrate noise. The p-type tap region comprises either (i) a plurality of generally bar shaped subregions disposed in parallel relation to n source subregions, or, (ii) a region that is generally annular in shape and surrounds the n&plus; source region. The p-type tap region functions to inhibit or prevent snapback of the ESD device, particularly inadvertent conduction of a parasitic lateral npn bipolar transistor, resulting from substrate noise during programming operations on an EPROM device or in general used in situations where high voltages close to but lower than the snapback voltage are required in the pin.

ESD structure having an improved noise immunity in CMOS and BICMOS semiconductor devices

An apparatus comprising a storage element coupled between a first and a second bond pad, the storage element having a physical characteristic that can be measured and altered. Data may be stored in the storage element by altering the physical characteristic.

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Snohomish, WA, United States of America

Mark W Rouse