United States of America As Represented by the Secretary of the Air Force

The United States of America

Mark W Levi

Daniel J Burns

Individual cells in a memory array are structured and interconnected to permit detection and identification of the locations of errors known as Single Event Upsets (SEUs), with the correction and identification of an affected cell made using only a single parity bit for a group of cells in a memory array, eliminating the necessity for reading an entire memory in order to detect SEUs immediately, and eliminate large numbers of non-useful correction-code cells in order to increase the net useful density of cells in a memory and tolerate a larger rate of SEU events than for previous methods, additionally eliminate the need for purification of packaging materials for memory arrays by removing most radioactive materials and providing a further economic benefit by eliminating the need for organic coatings, which can cause reliability hazards, and to block alpha particles originating in packaging.

Dynamic RAM (random access memory) with SEU (single event upset)

An alignment mark and pattern is disclosed for use on semiconductor substrates which are to be patterned in an electron lithography machine. The detector includes two interleaved N-well portions mounted on a P-substrate. The interleaved 'fingers' of the N-well portions are spaced to provide narrow gaps which are approximately the width of a projected electron beam. When the beam is located within the gap (or gaps) the projection is in alignment.

Field-symmetric beam detector for semiconductors

A dynamic random access memory circuit for storing an information signal using both a data input line and a data output line for a two-transistor dynamic ram cell memory circuit is disclosed. The circuit is incorporated into an integrated circuit array of similar cells. Because of the nature of the circuitry, the data input and output lines of each cell in the array are laid out in parallel, and the data-out line of one random access memory cell becomes the data-in line of the adjacent random access memory cell. Thus, while the addition of a separate line for data-in and data-out adds structure to a single cell, it reduces the overall structure of an array of such cells, and results in a more compact construction of a memory array.

Two-transistor dynamic random-access memory cell

A packaging apparatus used to store semiconductor devices with a coolant without contaminating the semiconductor devices. The apparatus has an enclosure which is evacuated at room temperature and then cooled in an atmosphere of coolant gas until the gas condenses and the enclosure is partially filled with liquid. The enclosure is then heated to allow the liquid to evaporate and a thermally activated mechanism to trap pure cold gas inside the enclosure. The trapped gas increases internal pressure which maintains a tight seal of the trapping mechanism against a gasket.

High dissipation packaging for cryogenic integrated circuits

A two transistor dynamic random access memory can be treated as a pair of voltage controlled elements which are reversibly controlled in a three step process. In the first step, a capacitance is charged on the controlling terminal of memory transistor. The second step entails isolating the charge on the capacitance of the controlling terminal. The third step entails providing a reversibly controlled voltage on the controlling terminal to further control the two memory transistors without altering the charge of the capacitance. This allows a non-destructive reading of the output of the stored information signal.

Two-transistor dynamic random-access memory cell having a common

An insulating film with low thermal expansion characteristics is formed by depositing aluminum alloy materials in thin film form without the use of high temperatures and which can then be oxidized to create an insulating film which has low stress. A mixture of aluminum and magnesium oxides, known as spinel, has the proportions which are approximately correct for zero expansion when crystallization results from the oxidation.

Stress reduced insulator

An electrostatic discharge protective apparatus for an integrated circuit having normally on semiconductor devices mutually connecting input/output pads and the power in bonding pad to prevent stray electrostatic discharges from damaging the integrated circuit components when the integrated circuit is not powered on. All adjacent input/output pads are connected to each other by a normally on transistor. Each pad is additionally connected to a power supply pad by a normally on transistor.

Electrostatic discharge protective circuit of shunting transistors

An apparatus for applying high current fast rise time pulses simulating electrostatic discharge (ESD) to various combinations of pins of a device under test (e.g., a microcircuit). The apparatus also provides for testing of the DUT after the performance of ESD stress testing. The apparatus establishes electrical connections between the terminals of a high voltage pulse generator (HVPG) and several different combinations of the DUT pins in sequence in order to apply ESD stresses. The apparatus further provides functional parameter tests whether the connection to the DUT pins during ESD stressing has caused the DUT to fail.

Apparatus for electrostatic discharge (ESD) stress/testing

A wafer cleaning system which cleans semiconductor wafers by sand blasting them with ice particles is disclosed. In this system a stream of gas is conducted by a conduit to the semiconductor wafer while a spray of water is frozen into the ice particles by a number of cooling coil systems which protrude into the conduit. After the semiconductor wafer is sandblasted with ice, any residual ice is removed simply by evaporating it. This results in a clean wafer without the contamination that can accompany chemical solvents of other semiconductor cleaning and etching systems.

Wafer cleaning method

An electro-optical crystal slab defining an optical waveguide modulator between two parallel boundary regions. Each boundary region has electrodes next to the channel and a doped area immediately outside the region. An electric field applied via the boundary electrodes creates a low index of refraction and transmitted light remains in the waveguide. When boundary fields are removed some light is absorbed by the doped material. Fields applied to compensating electrodes lower the index of refraction of the doped area so that the light is directed into it and absorbed. Any light passing through the absorbing material is contained in an alternate channel.

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Utica, NY, United States of America

Mark W Levi