Netapp, Inc.

Sun Microsystems, Inc.

Network Appliance, Inc.

Mark W Insley

Pradeep Kumar Kalra

Peter Snyder

Thomas Holland

Steven M Kurihara

R Guy Lauterbach

Jay C Robinson

Allen Kilbourne

Steve Valin

Dan H Gilson, Iii

Mitalee Gujar

Michael Rubin

Stephen Berry

Dan Gilson

A processing system includes control circuitry to control the processing system, a remote management module to enable remote management of the processing system via a network, and an agent to operate as an intermediary between the remote management module and the control circuitry. The agent and the remote management module are configured to cooperatively implement an abstraction layer through which the agent and the remote management module communicate.

Method and apparatus for communicating between an agent and a remote management module in a processing system

A remote management module (RMM) can be configured, in one embodiment, via the processing system that the RMM is monitoring. In one embodiment, the present invention includes allowing a user access to a processing system being monitored by a RMM, and configuring the RMM without the user accessing the RMM.

Configuring a remote management module in a processing system

According to an embodiment of the invention, a remote management device is integrated into a processing system, such as a filer or other storage server, and the remote management device and administrative data (such as console data) generated by the processing system are accessible even if the processing system becomes inoperable. The processing system includes a console port that outputs administrative data in the form of administrative data during system operation. The remote management device is accessible remotely, for example through a local area network (LAN) or a wide area network (WAN) such as the Internet, or a combination of networks. The remote management device intercepts the administrative data output by the console port and stores the data into memory on the remote management device.

Storage of administrative data on a remote management device

Provided is a method and system for protecting data transactions transmitted on an integrated circuit bus. Specifically, by transmitting data along with the complement of the data from one component to another component that are connected by the integrated circuit bus, the data and complemented data can be compared for errors. Exemplary errors include bit flips. Comparisons include logical operations, such as XOR, that determine if an error has occurred during the transmission of the data or complemented data on the integrated circuit bus.

Protecting data transactions on an integrated circuit bus

A system is provided including a host processing system and a remote management module coupled to it. The host processing system includes a boot storage device storing a plurality of boot images to allow the remote management module to remotely select a boot image from the plurality of boot images and to remotely cause the host processing system to boot utilizing the selected boot image.

Method and apparatus for boot image selection and recovery via a remote management module

A suspended or stuck condition of a serial bus controller is released by applying an artificial clock signal to the stuck bus controller in place of the normally applied clock signal. The artificial clock signal causes the stuck controller to advance in a communication transaction which was in progress when the stuck condition occurred, until a data signal is supplied at a logical level which permits the initiation of another transaction in accordance with the serial communication protocol of the bus. The ability to release the stuck condition avoids losing important data and other information that would be lost if the stuck condition was released by performing a reset of the stuck controller or the component to which it is connected.

Method and apparatus to release a serial bus from a suspended state

A computer system including a central processing unit (CPU) and a power management circuit (PMC). The CPU has an active mode where it is responsive to interrupt and direct memory access requests, and a standby mode where it is in a low power state and is not responsive to the interrupts and direct memory access requests. The PMC monitors the interrupts and direct memory access requests in the system when the CPU is in the standby mode, and causes the CPU to enter the active mode upon the detection of either an interrupt or a direct memory access request. The PMC includes: a standby register having a content which indicates either a standby or an active mode for the CPU; logic coupled to the standby register to produce a standby enabling output signal when the content of the standby register indicates a standby mode, and to produce a standby disabling output signal when the content of the standby register indicates an active mode; and logic which forces the content of the standby register to the active mode upon the detection of either an interrupt or a direct memory access request. A method for managing power consumed by a CPU of a computer system includes forcing the CPU to enter a low-power standby mode, monitoring the computer system for interrupts and direct memory access requests, and reactivating the central processing unit to an active mode where the CPU is capable of responding to the detected requests.

Method and apparatus for reducing power consumption in a computer system

The invention provides a method and apparatus for a memory device interface between a memory device and a CPU as well as the dimensions of the memory device. An electric circuit of the present invention has one-hundred-twenty pins along the length of the housing. The housing of the memory device has a length of approximately 85.6 mm and a width of approximately 54.0 mm. The left and right side socket interface portions of the housing have a minimum width of approximately 3.3 mm. The top socket interface portion has a maximum thickness of approximately 3.5 mm and a minimum height of approximately 3.0 mm. The bottom socket interface portion has a maximum thickness of approximately 5.0 mm and a minimum height of approximately 10.5 mm. Furthermore, the memory device interface portion of the present invention includes at least one pin which provides access to an address signal which indicates a memory array address location within the memory device. The interface portion also includes at least one pin which provides access to a data signal. Additionally, the interface portion includes a row address strobe signal which indicates that the address signal provided to the memory device is a row address, similarly at least one pin providing access to a column address strobe signal is included in the interface portion of the present invention. This column address strobe signal indicates that the address signal provided to the memory device is a column address. Further, at least one pin providing access to a memory write signal and at least one pin providing access to a memory output enable signal are included in the interface portion. Finally, the memory device interface of the present invention provides access to a power supply and to ground.

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Sunnyvale, CA, United States of America

Mark W Insley