Atmel Corporation

Mark W Heising

Michael John Sabin

A system and method for performing multiplication and modular reduction of large integers. The system includes at least one large integer unit, each large integer unit having a multiplier, an adder, and a register. First and second multiplier inputs are applied to the multiplier, and first and second adder inputs are applied to the adder. One output of the multiplier is also applied to the adder. A plurality of large integer units may be connected into a large integer unit array that includes a complementing gate and a latching register. A second output of the multiplier is applied to the first adder input of a next large integer unit, with processing speed increasing as additional large integer units are added to the array.

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Palo Alto, CA, United States of America

Mark W Heising