Vlsi Technology, Inc.

Koninklijke Philips Corporation N.V.

Mark W Haley

Delbert H Parks

Todd Mitchell

Albert H Liu

Judy U Galloway

The present invention is drawn to a method and a system for creating a sub-1V bandgap reference (BGR) circuit. In particular, a sub-1V BGR circuit is formed comprising a shallow trench isolation (STI) region and a poly silicon region above said STI region. The poly silicon region is formed having a first doped region longer than a second doped region. The poly silicon region as one single structure is adapted to function as a resistor and a diode coupled in series, said structure adapted to generate currents in a feedback loop to generate a BGR voltage. In forming the sub-1V BGR circuit, a silicide blocking mask (already available in the process flow for forming a standard semiconductor device) is used to prevent spacer oxide from forming above the center portion of the poly silicon region. In turn, silicide contacts can be formed away from the center portion of the poly silicon region.

Use of silicide blocking layer to create high valued resistor and diode for sub-1V bandgap

A method for cleaning bonding pads on a semiconductor device, as disclosed herein, includes treating the bonding pads with a CF and water vapor combination. In the process, the water vapor breaks up and the hydrogen from the water vapor couples to fluorine residue on the bonding pad surface creating a volatile HF vapor. In addition, fluorine from the CF exchanges with the titanium in the metallic polymer residue making the polymer more soluble for the organic strip operation which follows. Next, the resist is ashed and then an organic resist stripper is applied to the bonding pad area, thereby creating a clean bonding pad surface. Thereafter, a reliable bond wire connection can be made to the bonding pad.

Method for cleaning integrated circuit bonding pads

The present invention is directed to a method of forming an insulative layer over a fuse link in a semiconductor device that is sufficiently thick to encapsulate the fuse link during laser opening, thereby preventing vaporized metal from re-depositing on the fuse link. The layer is also sufficiently thin to allow the laser to penetrate the insulative layer during laser opening of the fuse. A primary dielectric layer is formed over a metal fuse link, the primary dielectric having a predetermined deposition thickness over the fuse link. The primary dielectric layer is then covered with an etch interrupting layer. The etch interrupting layer is covered with a secondary dielectric layer and a portion of the secondary dielectric layer is then removed, resulting in an interlayer dielectric (ILD) stack formed from the etch interrupting layer and the remaining secondary dielectric layer. The ILD has a selected thickness that is greater than the thickness of the primary dielectric layer. A metal layer is formed over the interlayer dielectric and then the layers over the etch interrupting layer and above the metal fuse link are then removed. Finally, the etch interrupting layer is removed from above the primary dielectric layer so as to expose a portion of the primary dielectric layer disposed above the metal fuse link.

Backend process for fuse link opening

An electrostatic chuck device for clamping a semiconductor wafer substrate during processing of the semiconductor wafer includes a power source, at least one negative pole, and a plurality of positive poles. Each positive pole selected from the plurality of positive poles is electrically separated from the negative pole. Also provided is a plurality of fuses, each fuse of the plurality of fuses is coupled to an associated positive pole included in the plurality of positive poles. Each fuse is further coupled to the power source. In some embodiments, each positive pole is electrically separated from the negative pole by an insulating epoxy. In other embodiments, the plurality of positive poles are connected to each other in parallel.

Multiple pole electrostatic chuck with self healing mechanism for wafer

A testing apparatus including a testing plate can be used to test an electrostatic wafer chuck. A DC potential is supplied so as to produce an electrostatic force. A mechanical force is supplied to the testing plate in order to give an indication of the produced electrostatic force. By examining the DC potential and the produced electrostatic force, an electrostatic wafer chuck can be qualified or rejected before being placed into a wafer processing machine. This reduces the possibility of damage to the wafer or the wafer processing machine.

Growing community of inventors

Rio Medina, TX, United States of America

Mark W Haley