Future Wei Technologies, Inc.

Synopsys, Inc.

Mark W Brown

Alan Gatherer

Debashis Bhattacharya

Alex Elisa Chandra

Ajay Singh Bisht

Ashish Rai Shrivastava

Peter Yan

Anup Kumar Sultania

Fang Yu

Hao Luan

Lee Dobson McFearin

Tong Sun

Ramakrishnan Balasubramanian

Xiaotao Chen

Yibing Wang

Jayanta Roy

Xingfeng Chen

Yan Bei

Ke Ning

Chushun Huang

Mehran Bagheri

Arney Deshpande

Embodiments relate to reading signals from a stimulus file produced by an emulator into a data store. A method includes executing, by a set of one or more worker processes, reading tasks. Each reading task is executable independent of other reading tasks. Each reading task includes reading a time slice of a signal from a stimulus file produced by a hardware emulator, and pushing a partial waveform corresponding to the time slice to a data store. The partial waveform includes a head and a tail that each has a smaller data size than an entirety of the partial waveform. The method further includes executing stitching tasks. The stitching tasks include pulling the heads and tails of the partial waveform from the data store, modifying the heads and tails to indicate a temporal order of the partial waveforms, and pushing the modified heads and tails back to the data store.

Memory efficient and scalable approach to stimulus (waveform) reading

Systems and methods for integrated circuit (IC) analysis using a multi-level data hierarchy implemented on a distributed compute and data infrastructure are described. An IC design may be represented using a set of storage areas, where each storage area may be stored in a contiguous block of storage and may correspond to a portion of the IC design. An analysis application may be executed on the IC design, where a subset of the set of storage areas that is used by the analysis application may be retrieved on-demand.

Integrated circuit analysis using a multi-level data hierarchy implemented on a distributed compute and data infrastructure

A data warehouse engine (DWE) includes a central processing unit (CPU) core and a first data organization unit (DOU), where the first DOU is configured to aggregate read operations. The DWE also includes a first command queue coupled between the CPU core and the first DOU, where the first command queue is configured to convey commands from the CPU core to the first DOU.

System and method for data warehouse engine

A computation system-on-a-chip (CSoC) includes a first scalable distributed real-time Data Warehousing (sdrDW) engine and a network interface coupled to the first sdrDW engine, where the network interface is coupled to an interconnect, and where the CSoC is configured to transmit a task request over the interconnect to a first networked bulk storage controller (NBSC) requesting that a task be performed on a bulk storage medium.

System and method for scalable distributed real-time data warehouse

A method includes receiving, by a real-time Data Warehouse (rDW) from a first task, a first dataset and spreading the first dataset to produce a first plurality of objects, where the first plurality of objects includes a first object and a second object. The method also includes storing the first object in a first location in an rDW data repository and storing the second object in a second location in the rDW data repository.

System and method for real-time data warehouse

Methods and apparatus for inter-process communication are provided. A circuit may have a plurality of clusters, and at least one cluster may have a computation element (CE), a memory operatively coupled with the CE, and an autonomic transport system (ATS) block operatively coupled with the CE and the memory. The ATS block may be configured to perform inter-process communication (IPC) for the at least one cluster. In one embodiment, the ATS block may transfer a message to a different cluster based on a request from the CE. In another embodiment, the ATS block may receive a message by allocating a buffer in the memory and write the message into the buffer. The ATS block may also be configured to manage synchronization and schedule tasks for the CE.

Scalable autonomic message-transport with synchronization

System and method embodiments are provided for messaging-based System-on-a-chip (SoC) power gating. The embodiments enable fine granularity SoC power gating without introducing significant latency and substantially maximizes SoC power reduction. In an embodiment, a method in a first SoC resource for messaging-based power gating includes receiving at the first SoC resource a wakeup notification message (WNM) from a second SoC resource, wherein the WNM comprises a time at which a result message from the second SoC resource is expected to arrive at the first SoC resource; determining with the first SoC resource a wake-up time according to the time at which the result message from the second SoC resource is expected to arrive at the first SoC resource; setting a wake-up time timer to expire at the wake-up time; and waking up the first SoC resource when the wake-up time timer expires when the first SoC resource is asleep.

Systems and methods for messaging-based fine granularity system-on-a-chip power gating

Growing community of inventors

Little Elm, TX, United States of America

Mark W Brown