National Semiconductor Corporation

Cyrix Corporation

Via-cyrix, Inc.

Mark W Bluhm

Raul A Garibay, Jr

Margaret R Herubin

Robert Maher

Mark W Hervin

Marvin Wayne Martinez, Jr

Steven C McMahan

Marc A Quattromani

Jeffrey S Byrne

Douglas Ewing Duschatko

David A Courtright

John K Eitrheim

William C Patton

Stanley D Harder

Douglas Beard

A pipelined computer system with power management control in accordance with one or both of a power management signal and a power management instruction.

Pipelined computer system with power management control

A power management method for a pipelined computer system in accordance with one or both of a power management signal and a power management instruction.

Power management method for a pipelined computer system

An instruction-initiated method for suspending operation of a pipelined data processor by selectively disabling a clock signal to pipeline subcircuitry in response to an instruction executed by the pipeline subcircuitry.

Instruction-initiated method for suspending operation of a pipelined data processor

An instruction-initiated power management method for a pipelined data processor by which a clock signal to pipeline subcircuitry is selectively disabled in response to an instruction executed by the pipeline subcircuitry.

Instruction-initiated power management method for a pipelined data processor

A signal-initiated method for suspending operation of a pipelined data processor by selectively disabling a clock signal to pipeline subcircuitry in response to at least one control signal.

Signal-initiated method for suspending operation of a pipelined data processor

A signal-initiated power management method for a pipelined data processor by which a clock signal to pipeline subcircuitry is selectively disabled in response to at least one control signal.

Signal-initiated power management method for a pipelined data processor

A pipelined data processor with instruction-initiated power management control in which a plurality of subcircuits, including pipeline subcircuitry and circuitry for generating and controlling at least one clock signal are responsive to an instruction executed by the pipeline subcircuitry by selectively disabling a clock signal to the pipeline subcircuitry.

Pipelined data processor with instruction-initiated power management control

A pipelined data processor with signal-initiated power management control in which a plurality of subcircuits, including pipeline subcircuitry, and circuitry for generating and controlling at least one clock signal are responsive to at least one control signal by disabling a clock signal to the pipeline subcircuitry.

Pipelined data processor with signal-initiated power management control

In accordance with the presently claimed invention, power consumption reduction control is provided to a processor used to execute instructions for data processing. A power management control signal is provided to the processor in accordance with conditions associated with the processor being operated in normal and reduced power consumption modes of operation, and an acknowledgement signal indicative of such reduced power consumption mode of operation is returned in correspondence with the power management control signal.

METHOD FOR CONTROLLING POWER OF A MICROPROCESSOR BY ASSERTING AND DE-ASSERTING A CONTROL SIGNAL IN RESPONSE CONDITIONS ASSOCIATED WITH THE MICROPROCESSOR ENTERING AND EXITING LOW POWER STATE RESPECTIVELY

Power consumption reduction control circuitry external and coupled to a processor used to execute instructions for data processing. A power management control signal is provided to the processor in accordance with conditions associated with the processor being operated in normal and reduced power consumption modes of operation, and an acknowledgement signal indicative of such reduced power consumption mode of operation is returned in correspondence with the power management control signal.

SYSTEM FOR CONTROLLING POWER OF A MICROPROCESSOR BY ASSERTING AND DE-ASSERTING A CONTROL SIGNAL IN RESPONSE TO CONDITION ASSOCIATED WITH THE MICROPROCESSOR ENTERING AND EXITING LOW POWER STATE RESPECTIVELY

A technique for invoking a low power operational mode in response to a halt instruction is used in a computer system that includes a processor coupled to external logic. The processor includes at least (i) a pipeline subcircuit to execute programmed instructions, including halt instructions, (ii) an interrupt handling subcircuit to handle interrupts generated by external interrupt logic, and (iii) clock generator circuitry that supplies clock signals to the pipeline and interrupt handling subcircuits. In response to execution of a halt instruction, the processor (i) enters the low power operational mode in which power consumption is reduced at least for the pipeline subcircuit, but without stopping the supply of clock signals to the interrupt handling subcircuit, and (ii) generates an acknowledgement signal to the external logic indicating that the clock signals to the pipeline subcircuit are being stopped, thereby entering the low power operational mode. In a preferred embodiment, the low power operational mode is entered by stopping the clock generator circuitry from supplying clock signals to the pipeline subcircuit, but not to the interrupt handling subcircuit. To resume normal processing, the interrupt handling subcircuit responds to an interrupt generated by the external logic by causing the clock generator circuitry to resume supplying clock signals to the pipeline subcircuit.

Method of invoking a low power mode in a computer system using a halt instruction

A circuit for diagnosing and debugging a processor for executing a stream of instructions that includes a set of debug registers for identifying an instruction or data address breakpoint; a processor for generating a debug exception in response to an instruction or data address in the stream of instructions matching the instruction or data breakpoint stored in the set of debug registers and a debug configuration register for enabling transfer of program control to one of a plurality of destinations in response to the debug exception. The debug configuration registers may designate system management mode, JTAG routine or a software debug interrupt handler as the destination.

Debug system allowing programmable selection of alternate debug mechanisms such as debug handler, SMI, or JTAG

A microprocessor comprises a plurality of instruction pipelines having a plurality of stages for processing a stream of instructions, circuitry for simultaneously issuing instructions into two or more of the pipelines without regard to whether one of the simultaneously issued instructions has a data dependency on other of the simultaneously issued instructions, detecting circuitry for detecting dependencies between instructions in the pipelines and circuitry for controlling the flow of instructions through the pipelines such that an instruction is not delayed due to a data dependency on another instruction unless the data dependency must be resolved for proper processing of the instruction in its current stage.

Processor with multiple execution pipelines using pipe stage state

A technique for invoking a low power operational mode in response to a halt instruction is used in a computer system that includes a processor coupled to external logic. The processor includes at least (i) a pipeline subcircuit to execute programmed instructions, including halt instructions, (ii) an interrupt handling subcircuit to handle interrupts generated by external interrupt logic, and (iii) clock generator circuitry that supplies clock signals to the pipeline and interrupt handling subcircuits. In response to execution of a halt instruction, the processor (i) stops the clock generator circuitry from supplying clock signals to the pipeline subcircuit, but not to the interrupt handling subcircuit, and (ii) generates an acknowledgement signal to the external logic indicating that the clock signals to the pipeline subcircuit are being stopped, thereby entering the low power operational mode. To resume normal processing, the interrupt handling subcircuit responds to an interrupt generated by the external logic by causing the clock generator circuitry to resume supplying clock signals to the pipeline subcircuit.

Computer system with low power mode invoked by halt instruction

A microprocessor comprises one or more instruction pipelines having a plurality of stages for processing a stream of instructions, with one or more of said instructions referencing a set of logical registers. A plurality of physical registers are allocated to store data associated with the logical registers by register translation circuitry. The register translation circuitry is selectively controlled by the microcode or by hardware signals generated by one or more of the stages.

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Plano, TX, United States of America

Mark W Bluhm