Integrated Device Technology, Inc.

Mosys, Inc.

Netlogic Microsystems, Inc

Mark W Baumann

Michael J Miller

John R Mick

Richard Stephen Roy

Jeff D Smith

Chuen-Der Lien

Chau-Chin Wu

Kee W Park

Robert J Proebsting

Scott Yu-Fan Chu

Stanley Hronik

Chris Schott

A chip layout for a high speed semiconductor device is disclosed. The chip layout isolates Rx terminals and Rx ports from Tx terminals and Tx ports. A serial interface is centrally located to reduce latency, power and propagation delays. Stacked die that contain one or more devices with the chip layout are characterized by having improved latency, bandwidth, power consumption, and propagation delays.

Semiconductor chip layout

Semiconductor chip layout with staggered Tx and Tx data lines

A chip layout isolates Rx terminals and Rx ports from Tx terminals and Tx ports. Tx terminals are grouped contiguously to each other, and are segregated as a group to a given edge of the package, Rx terminals are similarly grouped and segregated to a different edge of the package. Tx and Rx data channels are disposed in a respective single layer of the package, or both are disposed in a same single layer of the package. Rx ports and Tx ports are located at an approximate center of the package, with Tx and Rx ports disposed on respective opposite sides of an axis bisecting the package. Data signals received by, and transmitted from, the chip flow in a same direction, from a first edge of the package to the center of the package and from the center of the package to a second edge of the package, respectively.

Integrated circuit package with segregated Tx and Rx data channels

Content addressable memory (CAM) devices use both hard and soft priority techniques to allocate entries of different priority therein. The priorities of multiple CAM array blocks within the CAM device may be programmed before or as entries are loaded therein and may be reprogrammed during operation as the allocation of entries within the CAM device changes. The allocation of entries may change in response to additions or deletions of entries or as entries are reprioritized. The CAM devices include preferred priority resolution circuits that can resolve competing soft and hard priorities between multiple hit signals that are generated in response to a search operation. Such hit signals may be active to reflect the presence of at least one matching entry within a CAM array block. The resolution of which active hit signal has the highest overall priority among many can be used to facilitate the identification of the location (e.g., array address and row address) of a highest priority matching entry within the entire CAM device. A priority resolution circuit may also resolve competing hard priorities between two or more active hit signals having equivalent soft priority. This aspect of the priority resolution circuit is provided so that an active hit signal having a highest overall priority can be resolved whenever multiple CAM array blocks having the same soft priority are detected as having matching entries therein during a search operation.

Content addressable memory (CAM) devices having soft priority resolution circuits therein and methods of operating same

A method for processing addresses having variable prefix lengths, including (1) applying an input address to a plurality of CAM blocks; (2) assigning different sets of CAM blocks to store prefixes of different lengths; (3) generating a hit signal and an index signal with each of the CAM blocks in response to the input address; (4) programming a plurality of routing values; (5) routing the hit signals to a priority encoder in an order determined by the routing values; (6) generating an output hit signal with the priority encoder in response to the hit signals; (7) selecting one of the routing values as an index routing value in response to the output hit signal; and (8) routing one of the index signals as an output index value in response to the index routing value. Circuitry for implementing the method is also provided.

Content addressable memory array having flexible priority support

Content addressable memory (CAM) devices include error detection and correction (EDC) control circuits therein. The EDC control circuit operates to correct soft errors in entries within a plurality of internal CAM array blocks with, at most, limited interruption to other operations performed by the CAM device. The EDC control circuit utilizes a multi-bit check word associated with each entry to detect a soft error and perform one-bit error correction on the entry. The EDC control circuit is configured to be active during a background mode of operation when the CAM array blocks are undergoing search operations in a foreground mode of operation. A CAM array block may also include a column of dual-function check bit cells that are configured to operate as a column of CAM cells when necessary to replace a defective column of CAM cells.

Content addressable memory (CAM) devices having error detection and correction control circuits therein and methods of operating same

A CAM device includes an array of multi-compare port CAM cells therein. The CAM cells are configured to support concurrent search operations between multiple distinct search words and entries within the rows of the CAM array. These concurrent search operations may be performed in-sync with respective clock signals that are asynchronous relative to each other.

Content addressable memory (CAM) devices that utilize multi-port CAM cells and control logic to support multiple overlapping search cycles that are asynchronously timed relative to each other

A translation circuit for translating addresses between computer networks and an associated method of performing address translation for a computer system are provided. The translation circuit includes a content addressable memory (CAM) device having a CAM array that is logically divided into a plurality of CAM segments. First and second sets of CAM segments are designated to perform comparison operations for addresses having first and second widths, respectively. An instruction provided to the CAM device specifies an address translation having either the first or second width. A comparison operation is performed in the first set of segments if the instruction specifies an address translation of the first width. A comparison operation is performed in the second set of segments if the instruction specifies an address translation of the second width. In one embodiment, each segment has the same size, and includes a plurality of sub-segments, each having the same width.

Network translation circuit and method using a segmentable content addressable memory

A memory system including a memory array, an input circuit and a logic circuit is presented. The input circuit is coupled to receive a memory address and a set of individual write controls for each byte of data word. During a write operation, the input circuit also receives the corresponding write data to be written into the SRAM. The logic circuit causes the write data and write control information to be stored in the input circuit for the duration of any sequential read operations immediately following the write operation and then to be read into memory during a subsequent write operation. During the read operation, data which is stored in the write data storage registers prior to being read into the memory can be read out from the memory system should the address of one or more read operations equal the address of the data to be written into the memory while temporarily stored in the write data storage registers. The logic circuit also detects which bytes of data are not to be written into the SRAM so that, during a read operation, those bytes not to be written into the SRAM are read from the SRAM in order to output a complete word corresponding to the value at the read address. No &ldquo;bus turnaround&rdquo; down time is experienced by the system thereby increasing the bandwidth of the system. The system can operate in a single pipeline mode or a dual pipeline mode.

Separate byte control on fully synchronous pipelined SRAM

A quad data rate RAM ( ) in accordance with the invention is a burst synchronous RAM with separate data buses (Data-In, Data-Out) for read and write data. Data can be transferred on both buses and on both the rising and the falling edge of the clock (CLK). Operating at the maximum throughput, four data items are transferred per clock cycle. In one embodiment, data is written to or read from the RAM in bursts of four data items. The RAM includes four independent internal RAM blocks ( ). in a write burst, (i) a write address, (ii) control signal(s), and (iii) four write data items are sequentially presented to the respective four internal RAM blocks at the respective four clock edges of two consecutive clock cycles. A read burst is carried out similar to a write burst except that there is a one clock cycle latency between the four read data items and the burst address.

Quad data rate RAM

A memory device (,) having left (,) and right (,) ports for communicating with left (,) and right (,) electronic devices, includes memory banks (,-,-,), semaphore logic (,), and port coupling circuitry (,-,-,-,-,-,-,). The semaphore logic generates bank access grant signals (,) on a first received basis in response to bank access requests from the left and right electronic devices, and the port coupling circuitry couples selected memory banks to the left and right ports in response to the bank access grant signals. Also included in the memory device are mail-box registers (,-,L&tilde;,-,L,,-,R&tilde;,-,R), interrupt generating circuitry (,-,L&tilde;,-,L,,-,R&tilde;,-,R,,), and interrupt status and cause registers (,L&tilde;,L,,R&tilde;,R,,L&tilde;,L,,R&tilde;,R). The left and right electronic devices use the mail-box registers to send messages to each other without waiting. The interrupt generating circuitry generates interrupts to notify the left and right electronic devices when their bank access requests have been granted, and when a message has been written into one of the mail-box registers for them. The interrupt status and cause registers provide information as to which memory banks the left and right electronic devices have been granted access to, and which mail-box registers contain messages for them.

Multi-ported memory architecture using single-ported RAM

A memory system including a memory array, an input circuit and a logic circuit is presented. The input circuit is coupled to receive a memory address and a set of individual write controls for each byte of data word. During a write operation, the input circuit also receives the corresponding write data to be written into the SRAM. The logic circuit causes the write data and write control information to be stored in the input circuit for the duration of any sequential read operations immediately following the write operation and then to be read into memory during a subsequent write operation. During the read operation, data which is stored in the write data storage registers prior to being read into the memory can be read out from the memory system should the address of one or more read operations equal the address of the data to be written into the memory while temporarily stored in the write data storage registers.

A memory device (201) having left (203) and right (204) ports for communicating with left (205) and right (206) electronic devices, includes memory banks (401-0.about.401-7), semaphore logic (302), and port coupling circuitry (403, 404, 405-0.about.405-7, 406-0.about.406-7, 407-0.about.407-7). The semaphore logic generates bank access grant signals (313, 314) on a first received basis in response to bank access requests from the left and right electronic devices, and the port coupling circuitry couples selected memory banks to the left and right ports in response to the bank access grant signals. Also included in the memory device are mail-box registers (2500-0L.about.2500-3L, 2500-0R.about.2500-3R), interrupt generating circuitry (2514-0L.about.2514-3L, 2514-0R.about.2514-3R, 2900, 3000, 307, 308), and interrupt status and cause registers (3101L.about.3102L, 3101R.about.3102R, 3301L.about.3302L, 3301R.about.3302R). The left and right electronic devices use the mail-box registers to send messages to each other without waiting. The interrupt generating circuitry generates interrupts to notify the left and right electronic devices when their bank access requests have been granted, and when a message has been written into one of the mail-box registers for them. The interrupt status and cause registers provide information as to which memory banks the left and right electronic devices have been granted access to, and which mail-box registers contain messages for them.

Semaphore enhancement to allow bank selection of a shared resource

A memory system including a memory array, an input circuit and a logic circuit is presented. The input circuit is coupled to receive a memory address and a set of individual write controls for each byte of data word. During a write operation, the input circuit also receives the corresponding write data to be written into the SRAM. The logic circuit causes the write data and write control information to be stored in the input circuit for the duration of any sequential read operations immediately following the write operation and then to be read into memory during a subsequent write operation. During the read operation, data which is stored in the write data storage registers prior to being read into the memory can be read out from the memory system should the address of one or more read operations equal the address of the data to be written into the memory while temporarily stored in the write data storage registers. The logic circuit also detects which bytes of data are not to be written into the SRAM so that, during a read operation, those bytes not to be written into the SRAM are read from the SRAM in order to output a complete word corresponding to the value at the read address.

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Campbell, CA, United States of America

Mark W Baumann