Translogic Technology, Inc.

Other

Cadic Corporation

Mark W Acuff

Dzung Joseph Tran

Nam Tosuntikool

A digital electronic circuit having first and second sections. The first section is adapted to transmit one of N input signals. The second section is adapted to receive the signal transmitted by the first section and one or more control signals. The second section is configured to output either an inverse of the signal transmitted by the first section or a logical 0, or to output either an inverse of the signal transmitted by the first section or a logical 1. The second section also may be selectively configurable.

Digital electronic circuit for use in implementing digital logic functions

A digital circuit configured to receive three or more input signals and produce an output signal corresponding to either an XOR or XNOR of the input signals. In one embodiment of the invention, the circuit includes a first section connected in series with a second section to form a three-input XOR or XNOR gate. The first section is a two-input XOR or XNOR circuit having no more than eight transistors, including two transmission gate pairs. The second section is a two-input XOR or XNOR circuit having no more than six transistors, including one transmission gate pair.

Exclusive Or/Nor circuit

Exclusive or/nor circuit

A dynamic logic circuit that uses substantially constant power and that has substantially constant propagation delay, independent of the number of inputs the dynamic logic circuit contains. In one embodiment of the circuit, an evaluation transistor is positioned between a precharge transistor and a dynamic logic block. The evaluation transistor separates a precharge node from the logic block during a precharge clock phase so that the logic block is not charged. A delay coupled to the precharge transistor allows the precharge transistor to remain activated during a portion of an evaluation clock phase to overcome any effects of charge-sharing between the precharge node and the dynamic logic block. Because the evaluation transistor separates the logic block from the precharge node, the precharge node can be charged independently of the number of inputs present in the dynamic logic block.

Dynamic logic circuit

A level restore circuit used in MOS logic circuit design provides a voltage swing from a valid low to a valid high logic level in response to an input signal ranging from a degraded voltage high signal to a logic low signal. An input stage receives the degraded logic signal and provides separate gate drive signals to an inverter. An inverter in the intermediate stage receives the separate drive signals and provides an inverted signal output at a valid logic level. The intermediate stage also includes a pull-up device to pull up one of the gate nodes of the inverter to a logic high level. An output stage can optionally be coupled to the inverter to isolate it from a load.

Level restoration circuit for pass logic devices

A gate array architecture adapted for serial multiplexer-based circuits. In one embodiment, the gate array contains base cells having functional but isolated serial multiplexer circuits therein. In another embodiment, a base cell contains a single serial multiplexer circuit divisible into varying-sized (size corresponding to the number of inputs) derivative serial multiplexer circuits. In either embodiment, the serial multiplexer circuits within the base cell may be formed from P- and N-channel transistors of varying size. The transistor sizes are chosen to optimize the efficiency of serial multiplexer-based circuits.

Gate array with fully wired multiplexer circuits

A gate array architecture adapted for circuits containing transmission gates. In one embodiment, the gate array architecture contains a base row having at least four alternating P- and N-channel transistor rows. The transistor rows are positioned between a first voltage and a second voltage rail. In another embodiment, the rows adjacent the first and second voltage rails have larger transistors to facilitate connection of the transistors as inverters or buffers. The rows more remotely positioned from the first and second voltage rails have smaller transistor sizes to facilitate connection of the transistors as transmission gates. The gate array architecture is particularly efficient when used to create serial multiplexer-based circuits.

Gate array architecture for multiplexer based circuits

The present invention includes a device for providing connections to a plurality of inputs of a circuit to be tested. A computer stores test vectors comprising data representing stimulus signals to be applied to the circuit and data representing response signals to be sensed from the circuit. The stored test vectors are applied through a driver associated with each input of the circuit to be tested. The driver has an output capable of assuming a high state, a low state or a floating state. A driver control causes the driver to assume a high or low output state in response to data representing stimulus signals and causes the driver output to assume a floating state in response to data representing response signals. Response signals from the device to be tested are compared to the data representing response signals to determine the occurrence of a fault.

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Hillsboro, OR, United States of America

Mark W Acuff