Lsi Corporation

Agere Systems Inc.

Other

Avago Technologies General IP (singapore) Pte. Ltd.

Mark Trafford

Mohammad Shafiul Mobin

Ye Liu

Kenneth Wade Paist

Vladimir Sindalovsky

William Burdett Wilson

Amaresh Virupanagouda Malipatil

Steven E Strauss

Wilhelmus Diepstraten

Matthew Tota

Sunil Srinivasa

Aart Jan M Geurtsen

Tom Gibbons

Described embodiments provide for, in a receiver circuit, an adaptation process that adjusts the IQ-skew automatically to obtain proper eye centering in a data eye, thereby maximizing horizontal margin of the eye. The IQ-skew adaptation algorithm is realized with a 'biased' bang-bang phase detector (BBPD) oof a clock and data recovery circuit (CDR) that biases the weights applied to UP and DOWN outputs of the phase detector, rather than treating them equally. By weighting the BBPD UPs and DOWNs differently, the system locks to the left and right inner corners, and thereby is able to locate the center of the inner eye.

IQ-skew adaptation for a symmetric eye in a SerDes receiver

Methods and apparatus are provided for automatic gain control in a receiver using samples taken at a desired sampling phase and target voltage level. The gain of a received signal is adjusted by obtaining a plurality of samples of the received signal substantially at a desired sampling phase (such as a center of a given unit interval), wherein at least one of the samples is taken substantially at a target voltage level; comparing the plurality of samples to determine whether the received signal has an amplitude that is substantially equal to the target voltage level; and adjusting a receiver gain based on whether the received signal amplitude is substantially equal to the target voltage level. The comparison can comprise the evaluation of a logic function, such as an exclusive OR function. The comparison can be performed over a plurality of samples to obtain an average gain update decision. The receiver gain can be adjusted based on a histogram of the average gain update decision, relative to a predefined threshold.

Methods and apparatus for automatic gain control using samples taken at desired sampling phase and target voltage level

In described embodiments, a transceiver includes a clock and data recovery module (CDR) with an eye monitor and a cycle slip monitor. The cycle slip detector monitors a CDR lock condition, which might be through detection of slips in sampling and/or transition timing detection. The cycle slip detector provides a check point to sense system divergence, allowing for a mechanism to recover CDR lock. In addition, when the CDR is out-of-lock, the various parameters that are adaptively set (e.g., equalizer parameters) might be invalid during system divergence. Consequently, these parameters might be declared invalid by the system and not used.

Receiver training with cycle slip detection and correction

In described embodiments, filter parameters for a filter applied to a signal in, for example, a Serializer/De-serializer (SerDes) receiver and/or transmitter are generated based on real-time monitoring of a data eye. The real-time eye monitor monitors data eye characteristics of the signal present in a data path, the data path applying the filter to the signal. The eye monitor generates eye statistics from the monitored data eye characteristics and an adaptive controller generates a set of parameters for the filter of the data path for statistical calibration of the data eye, wherein the eye monitor continuously monitors the data eye and the adaptive controller continuously generates the set of parameters based on the eye statistics.

Real-time eye monitor for statistical filter parameter calibration

In described embodiments, adaptive equalization of a signal in, for example, Serializer/De-serializer transceivers by a) monitoring a data eye in a data path with an eye detector for signal amplitude and/or transition; b) setting the equalizer response of at least one equalizer in the signal path while the signal is present for statistical calibration of the data eye; c) monitoring the data eye and setting the equalizer during periods in which received data is allowed to contain errors (such as link initiation and training periods) and periods in which receive data integrity is to be maintained (such as normal data communication).

Statistically-adapted receiver and transmitter equalization

In one embodiment, a Universal Serial Bus (USB) system assigns a first priority level to a first USB endpoint and a second priority level that is lower than the first priority level to a second USB endpoint. The USB system has memory that stores first USB data packets corresponding to the first priority level and second USB data packets corresponding to the second priority level. The USB system also has a controller that manages transfers of (i) the first USB data packets to the first USB endpoint and (ii) the second USB data packets to the second USB endpoint. If the memory concurrently stores first and second USB data packets, then the controller determines an order for transferring the first and second USB data packets based on the second priority level being lower than the first priority level and/or detection of a starvation condition for the second endpoint.

Techniques for managing priority queues and escalation considerations in USB wireless communication systems

Methods and apparatus are provided for clock skew calibration in a clock and data recovery system. One aspect of the invention compensates for skew among a plurality of clocks in a clock and data recovery system. The clocks are applied to a plurality of latches to sample an incoming signal. A reference signal, such as a Nyquist signal, is applied to a data input of each of the latches. Statistics of 'early' and 'late' corrections applied to at least one of the clocks by a bang-bang phase detector in the clock and data recovery system are evaluated and a delay of a clock buffer associated with the at least one clock is adjusted to obtain approximately a 50% early-to-late ratio for the at least one clock. The clock and data recovery system ensures that the early-to-late ratio for the sum of the plurality of clocks is approximately 50%.

Method and apparatus for clock skew calibration in a clock and data recovery system using multiphase sampling

Various apparatus and methods for related to clock recovery are disclosed. For example, in one illustrative embodiment, a clock recovery circuit includes a coding circuit adapted to translate a stream of first digital numbers derived from a source signal into a stream of first binary numbers and a stream of second binary numbers, a digital-to-analog converter (DAC) circuit coupled to the coding circuit and configured to provide an analog output based on the streams of first and second binary numbers and a voltage-controlled oscillator (VCO) controlled by the analog output of the DAC circuit and adapted to produce a base clock having a base clock frequency.

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Fleetwood, PA, United States of America

Mark Trafford