Advanced Micro Devices Corporation

Dell Products Inc.

Mark Tracy Ellis

Richard G Russell

David Francis Tobias

Adolfo Sandor Montero

Lloyd W Gauthier

Gary Michael Godfrey

Daniel B Reents

Donald G Craycraft

An information handling system includes a power supply unit (PSU) and a motherboard. The PSU provides power to components of the information handling system, and includes power monitoring circuitry and digital-to-analog (D/A) circuitry. The power monitoring circuitry of the PSU determines whether the provided power exceeds one of a plurality of thresholds during a respective one of a plurality of time periods, and provides a digital value on one of a plurality of pins based on one of the threshold voltages being exceeded during the corresponding time period. The D/A circuitry of the PSU detects the digital value on one of the pins, and provides one of a plurality of quantized voltages. Each of quantized voltages corresponds to a different one of the pins. The motherboard receives the one of quantized voltages, and activates a throttling operation based on the received one of quantized voltages.

Real-time communication of power supply unit power loading status

Systems and methods for securely sharing a memory between an Embedded Controller (EC) and a Platform Controller Hub (PCH). In some embodiments, an IHS may include: a chipset; a flash device coupled to the chipset; and an EC coupled to the flash device via a first bus and to the chipset via a second bus, wherein the EC comprises a Read-Only Memory (ROM) portion and a Random Access Memory (RAM) portion, the EC configured to: retrieve EC firmware from the flash device via the first bus; store the retrieved EC firmware in the RAM portion; and prior to the execution of any instruction stored in the RAM portion, relinquish access to the flash device via the first bus.

Securely sharing a memory between an embedded controller (EC) and a platform controller hub (PCH)

A microcontroller has many internal peripheral devices. The peripheral devices are coupled to a scan path. A memory storage device that is external to the microcontroller is also coupled to the scan path. When commanded, data is shifted out of each device configuration register onto the scan path and stored in the external memory device. This is particularly useful for obtaining the states of each device without bringing down the application. Furthermore, configuration data stored in external memory can be loaded into the peripheral device configuration registers via the scan path. This invention also supports zero-volt suspend/resume which does not need extra software readable shadow registers which are often required in other architectures for reading back the current state of legacy registers which are read-only.

Method and apparatus for communicating configuration data for a peripheral device of a microcontroller via a scan path

Method and apparatus for saving peripheral device states of a microcontroller

The scalable virtual timer system or subsystem implements multiple hardware timers with minimal silicon overhead. In one embodiment, for each virtual timer of a plurality of virtual timers, a content addressable memory stores a sum of an &ldquo;initial state&rdquo; of a free running counter and a desired count duration for the virtual timer. When the stored value matches a current state of the free running counter, the content addressable memory generates a terminal count for the virtual timer. In an alternative embodiment, for each virtual timer, a period register of a set of period registers stores a sum of a desired count duration for a virtual timer and an &ldquo;initial state&rdquo; of the free running counter. A comparator of a set of comparators generates a terminal count for a virtual timer when a current state of the free running counter matches the sum stored in a period register associated with the virtual timer. A state of the free running counter may be read through software, such as by an execution unit, or through hardware, such as by an adder.

Scalable virtual timer architecture for efficiently implementing multiple hardware timers with minimal silicon overhead

Method and apparatus for saving and loading peripheral device states of a microcontroller via a scan path

A personal information device is provided, which includes an integrated circuit coupled to a variety of peripheral devices. The integrated circuit is configured with a core section and one or more input/output sections. The core section is powered independently of the input/output sections, allowing selective power down of peripheral components coupled to the integrated circuit without the use of external buffers. The input/output sections are configured with unique input/output circuits which perform the buffering task. The integrated circuit is further configured with a partial reset. The partial reset selectively forces portions of the integrated circuit to an initial state while other portions continue to operate. One particular embodiment of the integrated circuit is configured with a CPU and an RTC unit which comprises configuration RAM and a real time clock facility. When the partial reset is activated, the RTC unit is not reset but the CPU is reset. When the personal information device detects the need to conserve power, the power supply or a reset unit asserts the partial reset. Additionally, the power supply powers down selected peripheral components and the associated input/output driver sections while retaining power to the core section. Time/date and configuration information is therefore retained and power consumption is reduced.

Growing community of inventors

Austin, TX, United States of America

Mark Tracy Ellis