International Business Machines Corporation

Globalfoundries Inc.

Lam Research Corporation

Mark Todhunter Robson

Douglas C La Tulipe, Jr

Vijay Narayanan

Sivananda K Kanakasabapathy

Ying Di Zhang

Richard Stephan Wise

Eduard Albert Cartier

Renee Tong Mo

Vamsi Krishna Paruchuri

Kathryn Turner Schonenberg

Xi Li

Michelle Leigh Steen

James R Bowers

Rashmi Jha

Siyi Li

Robert C Hefty

Audrey Charles

A method of forming a high aspect ratio via opening through multiple dielectric layers, a high aspect ratio electrically conductive via, methods of forming three-dimension integrated circuits, and three-dimensional integrated circuits. The methods include forming a stack of at least four dielectric layers and etching the first and third dielectric layers with processes selective to the second and fourth dielectric layers, etching the second and third dielectric layers with processes selective to the first and second dielectric layers. Advantageously the process used to etch the third dielectric layer is not substantially selective to the first dielectric layer.

Method of fabricating ultra-deep vias and three-dimensional integrated circuits using ultra-deep vias

A method etching features through a stack of a silicon nitride layer over a silicon layer over a silicon oxide layer in a plasma processing chamber is provided. The silicon nitride layer is etched in the plasma processing chamber, comprising; flowing a silicon nitride etch gas; forming the silicon nitride etch gas into a plasma to etch the silicon nitride layer, and stopping the flow of the silicon nitride etch gas. The silicon layer is, comprising flowing a silicon etch gas, wherein the silicon etch gas comprises SFor SiF, forming the silicon etch gas into a, and stopping the flow of the silicon etch gas. The silicon oxide layer is etched in the plasma processing chamber, comprising flowing a silicon oxide etch gas, forming the silicon oxide etch gas into a plasma, and stopping the flow of the silicon oxide etch gas.

Silicon on insulator etch

The present invention relates to semiconductor devices, and more particularly to a process and structure for removing a dielectric spacer selective to a surface of a semiconductor substrate with substantially no removal of the semiconductor substrate. The method of the present invention can be integrated into a conventional CMOS processing scheme or into a conventional BiCMOS processing scheme. The method includes forming a field effect transistor on a semiconductor substrate, the FET comprising a dielectric spacer and the gate structure, the dielectric spacer located adjacent a sidewall of the gate structure and over a source/drain region in the semiconductor substrate; depositing a first nitride layer over the FET; and removing the nitride layer and the dielectric spacer selective to the semiconductor substrate with substantially no removal of the semiconductor substrate.

Dielectric spacer removal

Growing community of inventors

Danbury, CT, United States of America

Mark Todhunter Robson