Artisan Components, Inc.

Mark Templeton

Dhrumil Gandhi

An embedded memory device having improved BISR capabilities is provided. The embedded memory device includes an internal clock signal for use in accessing a memory array having access to redundant memory cells during normal operation, and a stress clock signal, wherein each pulse of the stress clock signal is of a shorter duration than each pulse of the internal clock signal. Further included are a built-in self-test circuit that performs a built-in self-test using the stress clock signal, and a register that stores defective memory addresses detected by the built-in self-test circuit. Redundant control logic is also included that redirects memory access operations to the defective memory addresses to redundant memory cells.

System and method for assured built in self repair of memories

A method and apparatus for improving the manufacturability of Integrated Circuits (ICs) formed on semiconductor dies is described. A plurality of different designs for some or all of the standard cells are made available to the circuit designer. Each different design may address a different problem associated with different manufacturing processes or a different design related yield limiter. Each of the design variants is characterized indicating its relative ease of manufacture, or it's yield sensitivity to certain IC design factors. The designer, typically with assistance from computer aided tools, can then select the standard cell variant for each of the cell used in the IC design that best addresses his or her design constraints. In other embodiments, variant versions of I/O cells and memory cells could also be created and made available to the designer in a similar fashion.

Yield maximization in the manufacture of integrated circuits

A method for testing a circuit is provided. The method includes providing a normal internal clock signal for use in accessing functional logic, where the functional logic has access to redundant functional logic during normal operation. The method then applies a stress clock signal to the functional logic, and each pulse of the stress clock signal is of a shorter duration than each pulse of the normal internal clock signal. Based on the applied stress clock signal, the method identifies logic elements of the functional logic that fail to operate as intended.

Method for identification of faulty or weak functional logic elements under simulated extreme operating conditions

A method for identifying faulty and weak memory cells is provided. A normal internal clock signal for use in accessing a memory array is provided, wherein the memory array may contain redundant memory cells that can be accessed during normal operation. In addition, a test is performed on the memory array using a stress clock signal. Each pulse of the stress clock signal is of a shorter duration than each pulse of the normal internal clock signal. In this manner, memory cells that fail the test using the stress clock signal are identified as non-usable memory cells. In some embodiments, the normal internal clock signal is based on required read and write times for the memory cells of the memory array and a margin added to the required read and write times. Each pulse of the stress clock signal can be approximately equal to each pulse of the normal internal clock signal minus the margin.

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Los Altos, CA, United States of America

Mark Templeton