Broadcom Corporation

Element 14, Inc.

Mark Taunton

Timothy Martin Dobson

Sophie Wilson

Andrew Jon Dawson

Timothy Dobson

Methods and systems for executing SIMD instructions that efficiently implement new SIMD instructions and conventional existing SIMD MAC-type instructions, while avoiding replication of functions in order to keep the size of the logic circuit size to as low a level as can reasonably be achieved. An instruction unit executes Single Instruction Multiple Data instructions, including instructions acting on operands representing complex numbers. The instruction unit includes functional blocks that are commonly utilized to execute a plurality of the instructions, wherein the plurality of instructions utilize various individual functional blocks in various combinations with one another. The plurality of instructions is optionally executed in a pipeline fashion.

Processor execution unit with configurable SIMD functional blocks for complex number operations

A system and method for efficiently performing bit-field extraction and bit-field combination operations in a processor is provided. The system includes a plurality of general purpose registers, a plurality of predicate registers, and at least one execution unit configured to extract a plurality of bit fields from a source reservoir and to populate a plurality of destination lanes in response to a single instruction. In addition, the execution unit is configured to write supplied fill data into the source reservoir if the number of bits in the source reservoir is less than a predetermined number. In addition or alternatively, the system may include at least one execution unit configured to combine a plurality of bit fields from a plurality of source lanes into a continuous bit stream in response to a single instruction executable by the processor.

System and method for efficiently performing bit-field extraction and bit-field combination operations in a processor

A method is used that substantially simultaneously trellis encodes data to be modulated onto multiple tones. The embodiments of the present invention comprise the steps of: (a) using a first input operand comprising state bits for a first trellis stage; (b) using a second input operand comprising a plurality of input data bits; and (c) generating an output comprising output data bits and output state bits from a first or later trellis stage.

DSL trellis encoding

A system and method for accelerated performance of quadrature amplitude modulation (QAM) is provided. The system includes multiple general purpose registers and multiple execution units configured to decode a set of QAM tones in parallel or an individual QAM tone in response to a single instruction executable by the processor. Each of the plurality of execution units is configured to decode one of the set of QAM tones according to a constellation size associated with the one of the set of QAM tones. The QAM decoding method includes reading a constellation size value for each of a set of received input tones. For each tone in the set of input tones, an ideal point in a QAM constellation of the associated constellation size closest to the X and Y coordinates of the tone is determined. The data values of the ideal points are then stored in a destination register.

System and method for accelerated performance of quadrature amplitude modulation (QAM) decoding operations in a processor

Systems and methods for implementing a zero overhead loop in a microprocessor or microprocessor based system/chip are disclosed. The systems and methods include the use of a breakpoint mechanism, and modification of parameters at runtime, with the breakpoint mechanism being additionally used in debugging, in order to provide some of the looping functionality.

System and method for implementing and utilizing a zero overhead loop

A system and method for accelerated handling of masked store operations in a processor or processor-based system/chip are described. A set of instructions that support a store operation under a per-byte predicate mask is provided. The invention accelerates the handling of small transfers at arbitrary alignments, such as those used by xDSL modems to deal with ATM cells or Reed Solomon codewords.

System and method for performing masked store operations in a processor

A Multi-tone transmission system processes input data through a plurality of intermediate processing stagesand corresponding stages of intermediate data. A symbol including a number of tones is obtained therefrom by an inverse Fourier transformand stored in a buffer. The peak amplitude that the symbol would contain after the subsequent processing in the analogue front endis modelled and compared to a threshold. If the modelled peak amplitude in the symbol exceeds the threshold, the symbol stored in bufferis regenerated. The symbols stored in the buffer are output through analogue front end

Multi-tone transmission

A method and apparatus are disclosed for efficiently scrambling one or more bytes of data according to DSL standards on a processor. This is achieved by providing an instruction for scrambling one or more bytes of data according to the DSL standards. Accordingly, the invention advantageously provides a processor with the ability to scramble data with a single instruction thus allowing for more efficient and faster scrambling operations for subsequent modulation and transmission.

Single instruction for data scrambling

A method and apparatus are disclosed for efficiently bit-reversing and scrambling one or more bytes of payload data according to DSL standards on a processor. In one embodiment, this is achieved by providing an instruction for bit reversing and scrambling one or more bytes of data according to the DSL standards. Accordingly, the invention advantageously provides a processor with the ability to bit reverse and scramble data with a single instruction thus allowing for more efficient and faster scrambling operations for subsequent modulation and transmission.

System and method for bit-reversing and scrambling payload bytes in an asynchronous transfer mode cell

A method and apparatus are disclosed for efficiently de-scrambling one or more bytes of data according to DSL standards on a processor. This is achieved by providing an instruction for de-scrambling one or more bytes of data according to the DSL standards. Accordingly, the invention advantageously provides a processor with the ability to de-scramble data with a single instruction thus allowing for more efficient and faster de-scrambling operations for subsequent processing.

Data de-scrambler

A method and apparatus are disclosed for efficiently de-scrambling and bit-order-reversing one or more bytes of data according to DSL standards on a processor. In a preferred embodiment, this is achieved by providing an instruction for de-scrambling and bit-order-reversing one or more bytes of data according to DSL standards. Accordingly, the invention advantageously provides a processor with the ability to de-scramble and bit-order-reverse data with a single instruction thus allowing for more efficient and faster de-scrambling operations for subsequent processing.

System and method for de-scrambling and bit-order-reversing payload bytes in an Asynchronous Transfer Mode cell

An FFT conversion instruction based on a single instruction multiple data ('SIMD') technique is executed to reduce the number of cycles for software to perform conversion processing used in an FFT computation. In an embodiment, the FFT conversion instruction implements two instances of a conversion operation, i.e., 2-way SIMD, over two sets of complex points at once. A control register or variant opcode controls an inverse flag to control the behavior of the conversion process. In an embodiment, the control register contains a control bit to select between forward and inverse FFT context.

System for executing SIMD instruction for real/complex FFT conversion

An FFT butterfly instruction based on single instruction multiple data ('SIMD') technique is executed to reduce the number of cycles for software to perform FFT butterfly operations. The FFT butterfly instruction can implement one or more instances of the FFT butterfly operation (e.g., non-SIMD, 2-way SIMD, 4-way SIMD, etc.), at once, each instance operating over a set of complex values. A control register or variant opcode controls the behavior of the FFT butterfly operation. The contents of the control register or the variant opcode can be altered to configure the butterfly behavior to suit specific circumstances. The FFT butterfly instruction can be used in the software on a processor in a chip-set implementing the central-office modem end of a DSL link. The FFT butterfly instruction can also be used in other contexts where an FFT function is performed (and/or where an FFT butterfly operation is used) including systems that do not implement DSL or DMT.

Method, system, and computer program product for executing SIMD instruction for flexible FFT butterfly

In an Asynchronous Transfer Mode cell, a method and apparatus are disclosed for producing a cell header having bytes with bits in reverse order. Address and control data bytes are received, and a value for a reverse bit Header Error Control byte is generated from the address and control data bytes. Additionally, the order of bits within each address and control data byte is reversed. The produced cell header comprises the reverse bit Header Error Control byte and the address and control data bytes with each address and control data byte having its bits in reversed order. In one embodiment, the present invention provides a processor instruction for producing the cell header having bytes with bits in reverse order. The instruction receives as input address and control data bytes. The instruction then computes a Header Error Control byte and formats the Header Error Control byte in reverse bit order for subsequent processing within the modem. Additionally, the instruction also reverses the bit-order of each byte of the cell header's address and control fields for subsequent processing within the modem.

System and method for generating header error control byte for Asynchronous Transfer Mode cell

A method for multiplying, at an execution unit of a processor, two complex numbers in which all four scalar multiplications, concomitant to multiplying two complex numbers, can be performed in parallel. A real part of a first complex number is multiplied at the execution unit by a real part of a second complex number to produce a first part of a real part of a third complex number. An imaginary part of the first complex number is multiplied at the execution unit by an imaginary part of the second complex number to produce a second part of the real part of the third complex number. A first arithmetic function is performed at the execution unit between the first part of the real part of the third complex number and the second part of the real part of the third complex number. The imaginary part of the first complex number is multiplied at the execution unit by the real part of the second complex number to produce a first part of an imaginary part of the third complex number. The real part of the first complex number is multiplied at the execution unit by the imaginary part of the second complex number to produce a second part of the imaginary part of the third complex number. A second arithmetic function is performed at the execution unit between the first part of the imaginary part of the third complex number and the second part of the imaginary part of the third complex number.

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Cambridge, United Kingdom

Mark Taunton