Advanced Micro Devices Corporation

Spansion Llc.

Other

Cypress Semiconductor Corporation

Fasl LLC

Fujitsu Corporation

Adesto Technologies Corporation

Nantero, Inc.

Infineon Technologies LLC

Fujitsu Amd Semiconductor Limited

Mark T Ramsbey

Yu Nan Sun

Angela Tai Hui

Tazrien Kamal

Sameer S Haddad

Tuan Duc Pham

Arvind Halliyal

Hidehiko Shiraiwa

Jean Y Yang

Chi K Chang

Nicholas H Tripsas

Minh Van Ngo

Shenqing Fang

Unsoon Kim

Chun Chen

Mark W Randolph

Yider Wu

Kuo Tung Chang

Jeffrey Allan Shields

Emmanuil Lingunis

Jaeyong Park

Jack F Thomas

Mark S Chang

Wei Zheng

Jean Yee-Mei Yang

Weidong Qian

Fei Wang

Zoran Krivokapic

Robert B Ogle

Michael Allen Van Buskirk

Kashmir S Sahota

James Minsu Pak

Fred T K Cheung

Dawn M Hopper

Narbeh Derhacobian

Ning Cheng

Ravi S Sunkavalli

Kouros Ghandehari

Jeff P Erhardt

David Michael Rogers

Jusuke Ogura

Janet S Wang

Kuo-Tung Chang

Vei-Han Chan

Rinji Sugino

Ashot Melik-Martirosian

Bharath Rangarajan

Matthew S Buynoski

Cyrus E Tabery

Timothy J Thurgate

Yi He

Daniel Sobek

David Keating Foote

Hsingya Arthur Wang

Stephen Keetai Park

Kathleen R Early

David H Matsumoto

Scott Allan Bell

Lu You

Hiroyuki Kinoshita

Richard J Huang

Suzette Keefe Pangrle

Marina V Plat

Effiong Etukudo Ibok

Venkatesh P Gopinath

Wenge Yang

Robert A Huertas

Hung-Sheng Chen

Satoshi Torii

Tatsuya Kajita

Carl Robert Huster

Maria Chow Chan

David H Chi

Michael David Fliesler

Nga-Ching Wong

Thomas Rueckes

Steven C Avanzino

Calvin T Gabriel

Michael K Templeton

Huicai Zhong

Eric N Paton

Darlene G Hamilton

Tatsuya Yamaguchi

Takashi Whitney Orimoto

George Jonathan Kluth

David K Liu

Yuan Tang

Joong Jeon

Lewis N Shen

Wenmei Li

Syuji Nozawa

John Dinh

Inkuk Kang

Hung-Eil Kim

Hirokazu Tokuno

Chakravarthy Gopalan

Edward Hsia

Edward Franklin Runnion

Anna Maria Minvielle

Ishai Naveh

A semiconductor device and method of making such device is presented herein. The method includes disposing a gate layer over a dielectric layer on a substrate and further disposing a cap layer over the gate layer. A first transistor gate is defined having an initial thickness substantially equal to a combined thickness of the cap layer and the gate layer. A first doped region is formed in the substrate adjacent to the first transistor gate. The cap layer is subsequently removed and a second transistor gate is defined having a thickness substantially equal to the thickness of the gate layer. Afterwards, a second doped region is formed in the substrate adjacent to the second transistor gate. The first doped region extends deeper in the substrate than the second doped region, and a final thickness of the first transistor gate is substantially equal to the thickness of the second transistor gate.

Split gate charge trapping memory cells having different select gate and memory gate heights

A semiconductor device and method of making the same are disclosed. The semiconductor device includes a memory gate on a charge storage structure formed on a substrate, a select gate on a gate dielectric on the substrate proximal to the memory gate, and a dielectric structure between the memory gate and the select gate, and adjacent to sidewalls of the memory gate and the select gate, wherein the memory gate and the select gate are separated by a thickness of the dielectric structure. Generally, the dielectric structure comprises multiple dielectric layers including a first dielectric layer adjacent the sidewall of the memory gate, and a nitride dielectric layer adjacent to the first dielectric layer and between the memory gate and the select gate. Other embodiments are also disclosed.

Memory first process flow and device

A method to fabricate a resistive change element. The method may include forming a stack over a substrate. The stack may include a conductive material, a resistive change material, a first surface, and a second surfaces opposite the first surface. The method may further include depositing a first material over the stack such that the first material directly contacts at least one of the first surface and the second surface of the stack. The method may also include after depositing the first material, forming a second material over the first material and evaporating a portion of the first material through the second material to create a gap between the second material and the at least one of the first surface and the second surface of the stack.

Resistive change elements using passivating interface gaps and methods for making same

An integrated circuit device can include a plurality of access transistors formed in a substrate having control terminals connected to word lines that extend in a first direction; a plurality of two-terminal programmable impedance elements formed over the substrate; at least one conductive plate structure formed on and having a common conductive connection to, the programmable impedance elements, and extending in at least the first direction; a plurality of storage contacts that extend from a first current terminal of each access transistor to one of the programmable impedance elements; a plurality of bit lines formed over the at least one conductive plate structure, the bit lines extending in a second direction different from the first direction; and a plurality of bit line contacts that extend from a second current terminal of each access transistor through openings in the at least one plate structure to one of the bit lines.

Memory device having programmable impedance elements with a common conductor formed below bit lines

A memory device can include a plurality of memory cells formed in a substrate, each having a resistive element programmable between at least two different resistance states, including memory cells configured to store data received by the memory device, and reference cells; a reference circuit formed in the substrate configured to generate at least a first reference resistance from resistances of a plurality of reference cells; a sense circuit formed in the substrate coupled to the memory cells and at least the first reference resistance and configured to compare a resistance of a selected memory cell to at least the first reference resistance to determine the data stored by the selected memory cell.

Reference circuits and methods for resistive memories

A split gate device that includes a memory gate and a select gate disposed side by side, a dielectric structure having a first portion disposed between the memory gate and a substrate and a second portion disposed along an inner sidewall of the select gate to separate the select gate from the memory gate, and a spacer formed over the select gate along an inner sidewall of the memory gate. Other embodiments of embedded split gate devices including high voltage and low voltage transistors are also disclosed.

Charge trapping split gate device and method of fabricating same

A semiconductor device that has a split gate charge trapping memory cell having select and memory gates of different heights is presented herein. In an embodiment, the semiconductor device also has a low voltage transistor and a high voltage transistor. In one embodiment, the gates of the transistors are the same height as the select gate. In another embodiment, the gates of the transistors are the same height as the memory gate.

Integrated capacitor structures and methods for fabricating same are provided. In an embodiment, the integrated capacitor structures exploit the capacitance that can be formed in a plane that is perpendicular to that of the substrate, resulting in three-dimensional capacitor structures. This allows for integrated capacitor structures with higher capacitance to be formed over relatively small substrate areas. Embodiments are suitable for use by charge pumps and can be fabricated to have more or less capacitance as desired by the application.

Three dimensional capacitor

Embodiments provide a split gate device, methods for fabricating a split gate device, and integrated methods for fabricating a split gate device and a periphery device. In an embodiment, the split gate device is a charge trapping split gate device, which includes a charge trapping layer. In another embodiment, the split gate device is a non-volatile memory cell, which can be formed according to embodiments as standalone or embedded with a periphery device.

Semiconductor devices and methods of manufacturing such devices are described herein. According to embodiments, the semiconductor device can be made by forming a dielectric layer at a first region and at a second region of a semiconductor substrate. A gate conductor layer is disposed over the dielectric formed in the first and the second regions of the semiconductor substrate, and the second region is masked. A split gate memory cell is formed in the first region of the semiconductor substrate with a first gate length. The first region is then masked, and the second region is etched to define a logic gate that has a second gate length. The first and second gate lengths can be different.

Charge trapping split gate embedded flash memory and associated methods

A semiconductor device includes a substrate comprising a source region and a drain region, a bit storing element formed on the substrate, a memory gate structure, a first insulating layer formed on the substrate, a second insulating layer formed on the substrate, and a select gate structure formed on the first insulating layer. The second insulating layer is formed on the memory gate structure and the select gate structure and between the memory gate structure and the select gate structure.

Use disposable gate cap to form transistors, and split gate charge trapping memory cells

Growing community of inventors

Sunnyvale, CA, United States of America

Mark T Ramsbey