Intel Corporation

Daedalus Prime LLC

Mark T Bohr

Tahir Ghani

Wilfred Gomes

Subhash M Joshi

Rajesh Kumar

Valery M Dubin

Anand S Murthy

Rishabh Mehandru

Mauro J Kobrinsky

Pooya Tadayon

Chia-Hong Jan

Patrick R Morrow

Nick Lindert

Robert L Sankman

Ebrahim Andideh

Annalisa Cappellani

Szuya S Liao

Walid M Hafez

Debendra Mallik

Ravindranath Vithal Mahajan

Swaminathan Sivakumar

Florian Gstrein

Rami Hourani

Fay Hua

Kevin J Lee

Jack T Kavalieros

Robert S Chau

Mark L Doczy

Andrew A Berlin

Altug Koker

Brian S Doyle

Willy Rachmady

Matthew V Metz

Johanna M Swan

Suman Datta

Justin K Brask

Glenn J Hinton

Biswajeet Guha

Kelin J Kuhn

Yih Wang

Bruce A Block

Sairam Agraharam

Ram S Viswanath

Valluri Ramana Rao

Stephen M Cea

Bernhard Sell

Manish Chandhok

Rui Ma

Edward Allyn Burton

Christopher P Auth

Joseph M Steigerwald

Jack Hwang

Jason W Klaus

Doug B Ingerly

Shahriar S Ahmed

Andrew W Yeoh

Stephen T Chambers

Ian R Post

Richard E Green

Mohsen Alavi

Sridhar Balakrishnan

Ruth Amy Brain

Harry Gomez

Barbara A Chappell

Joe F Walczyk

Marie Krysak

Harish Krishnamurthy

Cory C Bomberger

Mark Armstrong

Nadia M Rahhal-Orabi

Jun He

Abhijit Jayant Pethe

Christopher M Pelto

Scott E Thompson

Jose A Maiz

Dustin P Wood

Donald W Nelson

Robert W Martell

Sriram Srinivasan

Steven J Keating

Paul A Packan

Nachiket Venkappayya Desai

Sunit Tyagi

Kaizad Rumy Mistry

Eric A Karl

Richard Scott List

Thomas A Letson

Zheng Guo

Sanka Ganesan

Martin D Giles

Ibrahim Ban

Peter K Moon

Sanjay S Natarajan

Makarem A Hussein

Peter G Tolchinsky

Jeffrey K Greason

Anupama Bowonder

Ayan Kar

Kalyan C Kolluru

Julie A Tsai

Hyperchip structures and methods of fabricating hyperchips are described. In an example, an integrated circuit assembly includes a first integrated circuit chip having a device side opposite a backside. The device side includes a plurality of transistor devices and a plurality of device side contact points. The backside includes a plurality of backside contacts. A second integrated circuit chip includes a device side having a plurality of device contact points thereon. The second integrated circuit chip is on the first integrated circuit chip in a device side to device side configuration. Ones of the plurality of device contact points of the second integrated circuit chip are coupled to ones of the plurality of device contact points of the first integrated circuit chip. The second integrated circuit chip is smaller than the first integrated circuit chip from a plan view perspective.

Hyperchip

A semiconductor device having tipless epitaxial source/drain regions and a method for its formation are described. In an embodiment, the semiconductor device comprises a gate stack on a substrate. The gate stack is comprised of a gate electrode above a gate dielectric layer and is above a channel region in the substrate. The semiconductor device also comprises a pair of source/drain regions in the substrate on either side of the channel region. The pair of source/drain regions is in direct contact with the gate dielectric layer and the lattice constant of the pair of source/drain regions is different than the lattice constant of the channel region. In one embodiment, the semiconductor device is formed by using a dielectric gate stack placeholder.

Semiconductor device having tipless epitaxial source/drain regions

Gate contact structures disposed over active portions of gates and methods of forming such gate contact structures are described. For example, a semiconductor structure includes a substrate having an active region and an isolation region. A gate structure has a portion disposed above the active region and a portion disposed above the isolation region of the substrate. Source and drain regions are disposed in the active region of the substrate, on either side of the portion of the gate structure disposed above the active region. A gate contact structure is disposed on the portion of the gate structure disposed above the active region of the substrate.

Gate contact structure over active gate and method to fabricate same

A transistor comprises a substrate, a pair of spacers on the substrate, a gate dielectric layer on the substrate and between the pair of spacers, a gate electrode layer on the gate dielectric layer and between the pair of spacers, an insulating cap layer on the gate electrode layer and between the pair of spacers, and a pair of diffusion regions adjacent to the pair of spacers. The insulating cap layer forms an etch stop structure that is self aligned to the gate and prevents the contact etch from exposing the gate electrode, thereby preventing a short between the gate and contact. The insulator-cap layer enables self-aligned contacts, allowing initial patterning of wider contacts that are more robust to patterning limitations.

Self-aligned contacts

Uniform layouts for SRAM and register file bit cells are described. In an example, an integrated circuit structure includes a six transistor (6T) static random access memory (SRAM) bit cell on a substrate. The 6T SRAM bit cell includes first and second active regions parallel along a first direction of the substrate. First, second, third and fourth gate lines are over the first and second active regions, the first, second, third and fourth gate lines parallel along a second direction of the substrate, the second direction perpendicular to the first direction.

Uniform layouts for SRAM and register file bit cells

Gate-all-around integrated circuit structures having source or drain structures with epitaxial nubs, and methods of fabricating gate-all-around integrated circuit structures having source or drain structures with epitaxial nubs, are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires and a second vertical arrangement of horizontal nanowires. A first pair of epitaxial source or drain structures includes vertically discrete portions aligned with the first vertical arrangement of horizontal nanowires. A second pair of epitaxial source or drain structures includes vertically discrete portions aligned with the second vertical arrangement of horizontal nanowires. A conductive contact structure is laterally between and in contact with the one of the first pair of epitaxial source or drain structures and the one of the second pair of epitaxial source or drain structures.

Gate-all-around integrated circuit structures having source or drain structures with epitaxial nubs

Described herein are apparatuses, methods, and systems associated with a deep trench via in a three-dimensional (3D) integrated circuit (IC). The 3D IC may include a logic layer having an array of logic transistors. The 3D IC may further include one or more front-side interconnects on a front side of the 3D IC and one or more back-side interconnects on a back side of the 3D IC. The deep trench may be in the logic layer to conductively couple a front-side interconnect to a back-side interconnect. The deep trench via may be formed in a diffusion region or gate region of a dummy transistor in the logic layer. Other embodiments may be described and claimed.

Deep trench via for three-dimensional integrated circuit

Multi version library cell handling and integrated circuit structures fabricated therefrom are described. In an example, an integrated circuit structure includes a plurality of gate lines parallel along a first direction of a substrate and having a pitch along a second direction orthogonal to the first direction. A first version of a cell type is over a first portion of the plurality of gate lines, the first version of the cell type including a first plurality of interconnect lines having a second pitch along the second direction, the second pitch less than the first pitch.

Multi version library cell handling and integrated circuit structures fabricated therefrom

Integrated circuit (IC) cell architectures including a crenellated interconnect trace layout. A crenellated trace layout may be employed where an IC cell includes transistor having a source/drain terminal interconnected through a back-side (3D) routing scheme that reduces front-side routing density for a given transistor footprint. In the crenellated layout, adjacent interconnect traces or tracks may have their ends staggered according to a crenellation phase for the cell. Crenellated tracks may intersect one cell boundary with adjacent tracks intersecting an opposite cell boundary. Track ends may be offset by at least the width of an underlying orthogonal interconnect trace. Crenellated track ends may be offset by the width of an underlying orthogonal interconnect trace and half a spacing between adjacent orthogonal interconnect traces.

Integrated circuit device with crenellated metal trace layout

Systems and methods for providing a low profile stacked die semiconductor package in which a first semiconductor package is stacked with a second semiconductor package and both semiconductor packages are conductively coupled to an active silicon substrate that communicably couples the first semiconductor package to the second semiconductor package. The first semiconductor package may conductively couple to the active silicon substrate using a plurality of interconnects disposed in a first interconnect pattern having a first interconnect pitch. The second semiconductor package may conductively couple to the active silicon substrate using a plurality of interconnects disposed in a second interconnect pattern having a second pitch that is greater than the first pitch. The second semiconductor package may be stacked on the first semiconductor package and conductively coupled to the active silicon substrate using a plurality of conductive members or a plurality of wirebonds.

Package on active silicon semiconductor packages

The present disclosure is directed to systems and methods of conductively coupling a plurality of relatively physically small core dies to a relatively physically larger base die using an electrical mesh network that is formed in whole or in part in, on, across, or about all or a portion of the base die. Electrical mesh networks beneficially permit the positioning of the cores in close proximity to support circuitry carried by the base die. The minimal separation between the core circuitry and the support circuitry advantageously improves communication bandwidth while reducing power consumption. Each of the cores may include functionally dedicated circuitry such as processor core circuitry, field programmable logic, memory, or graphics processing circuitry. The use of core dies beneficially and advantageously permits the use of a wide variety of cores, each having a common or similar interface to the electrical mesh network.

Distributed semiconductor die and package architecture

Described herein are integrated circuit (IC) structures, devices, and methods associated with device layer interconnects. For example, an IC die may include a device layer including a transistor array along a semiconductor fin, and a device layer interconnect in the transistor array, wherein the device layer interconnect is in electrical contact with multiple different source/drain regions of the transistor array.

Device layer interconnects

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Aloha, OR, United States of America

Mark T Bohr