Nxp B.v.

Mark Stoopman

Erik Olieman

Helmut Kranabenter

Peter Van Der Cammen

Marcel Van De Gevel

Koen Van Hartingsveldt

Federico Bruccoleri

A low-pass filter circuit comprising: a low-pass filter input terminal; a low-pass filter output terminal; a reference terminal; at least three filter resistors connected in series with each other between the low-pass filter input terminal and the low-pass filter output terminal, such that there is a resistor-connecting-node between each adjacent pair of filter resistors; a plurality of filter capacitors, one for each of the resistor-connecting-nodes, wherein each of the filter capacitors is connected between an associated resistor-connecting-node and the reference terminal; and a branch connected in parallel with the at least three filter resistors, wherein the branch comprises a bridging capacitor and a bridging resistor in series with each other.

Low-pass filter circuit

A duty cycle correction (DCC) circuit for use in relation to differential signal communications, a method of providing duty cycle correction, and communications systems and methods employing same, are disclosed herein. In one example embodiment, the circuit includes a differential signal inverter circuit including first and second inverter circuits, each of which has a respective inverter and respective first and second transistor devices respectively coupled between the respective inverter and first and second voltages, respectively. The circuit also includes a feedback circuit coupled to respective output ports of the respective first and second inverter circuits and also to respective feedback input ports of the respective transistor devices. The feedback circuit operates to provide one or more feedback signals causing one or more of the transistor devices to perform current limiting. Respective duty cycles of output signals respectively are equal or substantially equal based on the current limiting.

Circuit to correct duty cycle and phase error of a differential signal with low added noise

A four-phase (or multi-phase) generation circuit, related method of operation, and transceivers or other systems utilizing such a circuit, are disclosed herein. In one example embodiment, the circuit includes two input ports respectively configured to receive positive and negative differential input signals, and four output ports respectively configured to output first, second, third and fourth output signals, respectively, the second, third, and fourth output signals being respectively phase-shifted relative to the first output signal by or substantially by 90, 180, and 270 degrees. Also, the circuit includes four SR latches respectively including output terminals that are respectively coupled to the respective output ports. Further, the circuit includes two tunable delay circuits respectively coupled at least indirectly between the input ports and latches, and two comparison circuits configured to output respective feedback signals. The latches receive two delayed input signals provided by the delay circuits based upon the feedback signals.

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Capelle aan den Ijssel, Netherlands

Mark Stoopman