Cadence Design Systems, Inc.

Mark Steven Hahn

Laurent Volpe

Guruprasad G Rao

Arnold Ginetti

Limin He

Harish Kriplani

Jimmy Kwok-Ching Lam

Naser Awad

Chris Morrison

A method and an apparatus are described for allowing several different applications to incrementally collaborate while making changes to a circuit design.

Change tracking and incremental synchronization of EDA design and technology data

Disclosed is an improved approach for managing, tracking, and querying hierarchical data in layouts. According to some aspects, hierarchical grids are employed utilizing a scheme that organizes physical objects into a set of gradually refined grids that avoids the need to maintain duplicates while enhancing the desirable characteristics of existing schemes, including fast query times, fast data structure initialization and reduced memory footprint. Each grid-cell may be further partitioned into sub-containers to more efficiently provide space pruning during query operations. According to one approach, structures maintained to track existence of objects in a descendent hierarchy.

Method and mechanism for managing hierarchical data for implementing region query

Method and mechanism for implementing region query using hierarchical grids

Method and mechanism for performing region query using hierarchical grids

Method and mechanism for maintaining existence information for electronic layout data

A method for generating a model for a circuit having logic components is provided. The method includes identifying interface path logic components of the logic components so as to define shell logic, and identifying at least one of the logic components on which a constraint has been annotated so as to define constrained logic components. A subset of the logic components to preserve is then determined, the subset including the shell logic and the constrained logic components so as to define preserved logic. The model is then formed from the preserved logic. A highly accurate model can thus be created, while reducing computational and memory requirements. On-the-fly regeneration of the model is also possible, as is dominant path logic preservation.

Method and system for logic-level circuit modeling

A method for timing verification of very large scale integrated circuits reduces required CPU speed and memory usage. The method involves steps including partitioning the circuit into a plurality of blocks and then partitioning the verification between shell path components and core path components. Timing verification is then conducted for only shell path components while core path components are abstracted or ignored. Finally, timing verification for core path components in each block completes the process for the entire design.

Timing verification method employing dynamic abstraction in core/shell partitioning

An integrated circuit design is divided into partitions which each contain two stages of information. The first stage corresponds to sources within the design, and the second stage corresponds to targets within the design. In one implementation, all of the sources in each partition are triggered by a common clock edge. In another implementation, all targets of each partition are triggered by a common clock edge. Specifying timing constraints in partitions can provide an efficient method of determining how much slack, if any, is present in the timing of a design.

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Milpitas, CA, United States of America

Mark Steven Hahn