Intel Corporation

Mark Stettler

Martin D Giles

Rafael Rios

Borna Obradovic

Jack T Kavalieros

Tahir Ghani

Robert S Chau

Brian S Doyle

Matthew V Metz

Mark L Doczy

Suman Datta

Justin K Brask

Mark T Bohr

Gerhard Schrom

Cory E Weber

Paul A Packan

Ian R Post

Shahriar S Ahmed

Scott E Thompson

Been Y Jin

Everett X Wang

Lucian Shifren

Philippe Matagne

A transistor may be formed of different layers of silicon germanium, a lowest layer having a graded germanium concentration and upper layers having constant germanium concentrations such that the lowest layer is of the form SiGe. The highest layer may be of the form SiGeon the PMOS side. A source and drain may be formed of epitaxial silicon germanium of the form SiGeon the PMOS side. In some embodiments, x is greater than y and z is greater than x in the PMOS device. Thus, a PMOS device may be formed with both uniaxial compressive stress in the channel direction and in-plane biaxial compressive stress. This combination of stress may result in higher mobility and increased device performance in some cases.

Complementary metal oxide semiconductor integrated circuit using uniaxial compressive stress and biaxial compressive stress

A method including forming a transistor device having a channel region; implanting a first halo into the channel region; and implanting a second different halo into the channel region. An apparatus including a gate electrode formed on a substrate; a channel region formed in the substrate below the gate electrode and between contact points; a first halo implant comprising a first species in the channel region; and a second halo implant including a different second species in the channel region.

Indium-boron dual halo MOSFET

Method and structure to decrease area capacitance within a buried insulator device structure are disclosed. A portion of the substrate layer of a buried insulator structure opposite the insulator layer from the gate is doped with the same doping polarity as the source and drain regions of the device, to provide reduced area capacitance. Such doping may be limited to portions of the substrate which are not below the gate.

Method and structure to decrease area capacitance within a buried insulator device

Method to form a structure to decrease area capacitance within a buried insulator device structure is disclosed. A portion of the substrate layer of a buried insulator structure opposite the insulator layer from the gate is doped with the same doping polarity as the source and drain regions of the device, to provide reduced area capacitance. Such doping may be limited to portions of the substrate which are not below the gate.

Method to form a structure to decrease area capacitance within a buried insulator device

An improved well boosting implant which provides better characteristics than traditional halo implants particularly for short channel devices (e.g., 0.25 microns or less). In effect, an implant is distributed across the entire channel with higher concentrations occurring in the center of the channel of the devices having gate lengths less than the critical dimension. This is done by using very large tilt angles (e.g., 30-50.degree.) with a relatively light dopant species and by using a relatively high energy when compared to the traditional halo implants.

Channel dopant implantation with automatic compensation for variations

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Hillsboro, OR, United States of America

Mark Stettler