Texas Instruments Corporation

Mark Stephen Toth

Terry Lee Sculley

Scott Robert Summerfelt

Wei-Yan Shih

David Hernandez

Alok Kumar Lohia

Steve Kummerl

Seung Bae Lee

Mandy Barsilai

Shawn Xianggang

An integrated force sensing element includes a piezoelectric sensor formed in an integrated circuit (IC) chip and a strain gauge at least partially overlying the piezoelectric sensor, where the piezoelectric sensor is able to flex. A human-machine interface using the integrated force sensing element is also disclosed and may include a conditioning circuit, temperature gauge, FRAM and a processor core.

Piezoelectric sensor apparatus

An integrated force sensing element includes a piezoelectric sensor formed in an integrated circuit (IC) chip and a strain gauge at least partially overlying the piezoelectric sensor, where the piezoelectric sensor is able to flex. A human-machine interface using the integrated force sensing element may include a conditioning circuit, temperature gauge, FRAM and a processor core.

Integrated force sensing element

Disclosed examples include methods and circuits to drive a haptic actuator, in which a single input signal from a host device has a first state representing a command to drive the actuator and a second state representing a command to stop the actuator. A control circuit provides a drive control signal to a driver circuit to drive the haptic actuator in response to the control signal transitioning to the first state, and to stop the haptic actuator in response to the control signal transitioning to the second state. A timer circuit places the circuit in a low power mode a predetermined time after the control signal transitions to the second state, or the control circuit places the circuit in the low power mode in response to a feedback signal indicating that the actuator has reached a stopped condition.

Integrated circuit with single wire haptic vibration control and selective open loop operation

A low-power data conversion system for converting a serial digital data input signal (DIN) to an analog output signal (Vout) by generating the serial digital data input signal (DIN) at a first sample rate (fsin) in a burst mode, wherein the sampling frequency of the serial digital data input signal (DIN) has a predetermined ratio to the frequency of an external reference clock signal (SLEEPCLK or WCLK). The serial digital data input signal (DIN) is converted into parallel format. A FIFO system temporarily stores a predetermined number of samples (Din) of the parallel format digital data input signal. The samples (Din) have a first sample rate (fsin). The samples (Din) are converted to an analog output signal (Vout).

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Murphy, TX, United States of America

Mark Stephen Toth