Samsung Electronics Co., Ltd.

Texas Instruments Corporation

Rodder Technologies, Inc.

University of Texas System

Mark Stephen Rodder

Borna Josip Obradovic

Joon Goo Hong

Jorge A Kittl

Wei-E Wang

Rwik Sengupta

Titash Rakshit

Robert Christopher Bowen

Dharmendar Reddy Palle

Ganesh Hegde

Ryan M Hatcher

Chris Bowen

Vassilios Gerousis

Mahalingam Nandakumar

Amitava Chatterjee

Kang-ill Seo

Manoj Mehrotra

Richard A Chapman

Rick L Wise

Harsono S Simka

Ih-Chin Chen

Robert M Wallace

Keith Alan Joyner

Jarvis Benjamin Jacobs

William U Liu

Kevin Michael Traynor

Xiaoye Qin

Tanya Abaya

Seung Hun Lee

Zhiqiang (Jeff) Wu

Robert H Havemann

Taylor R Efland

Seetharaman Sridhar

Amitabh Jain

Dong-won Kim

Douglas Ticknor Grider

David Seo

John Neal Randall

Matthew S Berzins

Purnendu K Mozumder

James R Hellums

Sunil V Hattangady

Chin-Yu Tsai

Alec James Morton

Andrew Paul Hoover

Puneet Kohli

E Ajith Amerasekera

Youngmin Kim

Pan Kwi Park

Katherine E Violette

Seung Ryul Lee

Jiann Liu

Vincent Maurice McNeil

Jerry Che-Jen Hu

Kiyotaka Imai

Christopher Bowen

Kota Oikawa

Kim Changhwa

Sam Tower

Mohammad Ali Pourghaderi

Palle Dharmendar

Ganesh Hedge

Zhiqiang Jeff Wu

A neuromorphic device for the analog computation of a linear combination of input signals, for use, for example, in an artificial neuron. The neuromorphic device provides non-volatile programming of the weights, and fast evaluation and programming, and is suitable for fabrication at high density as part of a plurality of neuromorphic devices. The neuromorphic device is implemented as a vertical stack of flash-like cells with a common control gate contact and individually contacted source-drain (SD) regions. The vertical stacking of the cells enables efficient use of layout resources.

High-density neuromorphic computing element

A method of manufacturing an integrated circuit having buried power rails includes forming a first dielectric layer on an upper surface of a first semiconductor substrate, forming a series of power rail trenches in an upper surface of the first dielectric layer, forming the buried power rails in the series of power rail trenches, forming a second dielectric layer on the upper surface of the first dielectric layer and upper surfaces of the buried power rails, forming a third dielectric layer on a donor wafer, bonding the third dielectric layer to the second dielectric layer, and forming a series of semiconductor devices, vias, and metal interconnects on or in the donor wafer. The buried power rails are encapsulated by the first dielectric layer and the second dielectric layer, and the buried power rails are below the plurality of semiconductor devices.

Integrated circuit with buried power rail and methods of manufacturing the same

A semiconductor cell block includes a series of layers arranged in a stack. The layers include one or more first layers each having a first height and one or more second layers each having a second height. The second height is larger than the first height, and the second height is a non-integer multiple of the first height. The semiconductor cell block also includes a first semiconductor logic cell having a first cell height in one of the series of layers, and a second semiconductor logic cell having a second cell height in one of the series of layers. The second cell height is larger than the first cell height, and the second cell height is a non-integer value multiple of the first cell height.

Semiconductor cell blocks having non-integer multiple of cell heights

A field-effect transistor (FET) device having a modulated threshold voltage (Vt) includes a source electrode, a drain electrode, a channel region extending between the source electrode and the drain electrode, and a gate stack on the channel region. The gate stack includes an ultrathin dielectric dipole layer on the channel region configured to shift the modulated Vt in a first direction, a high-k (HK) insulating layer on the ultrathin dielectric dipole layer, and a doped gate metal layer on the HK insulating layer configured to shift the modulated Vt in a second direction.

Method of forming multiple-Vt FETS for CMOS circuit applications

A neuromorphic multi-bit digital weight cell configured to store a series of potential weights for a neuron in an artificial neural network. The neuromorphic multi-bit digital weight cell includes a parallel cell including a series of passive resistors in parallel and a series of gating transistors. Each gating transistor of the series of gating transistors is in series with one passive resistor of the series of passive resistors. The neuromorphic cell also includes a series of programming input lines connected to the series of gating transistors, an input terminal connected to the parallel cell, and an output terminal connected to the parallel cell.

Multi-bit, SoC-compatible neuromorphic weight cell using ferroelectric FETs

A monolithic three-dimensional integrated circuit including a first device, a second device on the first device, and a thermal shield stack between the first device and the second device. The thermal shield stack includes a thermal retarder portion having a low thermal conductivity in a vertical direction, and a thermal spreader portion having a high thermal conductivity in a horizontal direction. The thermal shield stack of the monolithic three-dimensional integrated circuit includes only dielectric materials.

Method of forming a thermal shield in a monolithic 3-d integrated circuit

A method provides a gate structure for a plurality of components of a semiconductor device. A silicate layer is provided. In one aspect, the silicate layer is provided on a channel of a CMOS device. A high dielectric constant layer is provided on the silicate layer. The method also includes providing a work function metal layer on the high dielectric constant layer. A low temperature anneal is performed after the high dielectric constant layer is provided. A contact metal layer is provided on the work function metal layer.

Method of forming multi-threshold voltage devices and devices so formed

A semiconductor device includes a series of metal routing layers and a complementary pair of planar field-effect transistors (FETs) on an upper metal routing layer of the metal routing layers. The upper metal routing layer is M3 or higher. Each of the FETs includes a channel region of a crystalline material. The crystalline material may include polycrystalline silicon. The upper metal routing layer M3 or higher may include cobalt.

Semiconductor device including a repeater/buffer at upper metal routing layers and methods of manufacturing the same

A hardware cell and method for performing a digital XNOR of an input signal and weights are described. The hardware cell includes input lines, a plurality of pairs of magnetic junctions, output transistors and at least one selection transistor coupled with the output transistors. The input lines receive the input signal and its complement. The magnetic junctions store the weight. Each magnetic junction includes a reference layer, a free layer and a nonmagnetic spacer layer between the reference layer and the free layer. The free layer has stable magnetic states and is programmable using spin-transfer torque and/or spin-orbit interaction torque. The first magnetic junction of a pair receives the input signal. The second magnetic junction of the pair receives the input signal complement. The output transistors are coupled with the magnetic junctions such that each pair of magnetic junctions forms a voltage divider. The output transistors form a sense amplifier.

Method and system for providing a variation resistant magnetic junction-based XNOR cell usable in neuromorphic computing

Method of manufacturing an integrated circuit with buried power rail

Apparatus and method are provided. The apparatus includes at least one field effect transistor (FET), wherein the at least one FET comprises at least one gate overlaying at least one non-linear fin, wherein the non-linear fin is formed via modulating a mandrel by producing cut-outs in the mandrel via optical proximity correction (OPC). The method includes receiving a semiconductor wafer, forming source and drain areas for each of at least one FET on the semiconductor wafer; and forming at least one gate overlaying at least one non-linear fin in each of the at least one FET, wherein the non-linear fin is formed via modulating a mandrel by producing cut-outs in the mandrel via OPC.

Apparatus and method of modulating threshold voltage for fin field effect transistor (FinFET) and nanosheet FET

Growing community of inventors

Dallas, TX, United States of America

Mark Stephen Rodder