Microsoft Technology Licensing, LLC

Advanced Micro Devices Corporation

Ati Technologies Ulc

Silicon Graphics, Incorporated

Ati Technologies Inc.

Other

Mark Stefan Grossman

Stephen L Morein

Jason Matthew Gould

Ivan Nevraev

Martin J I Fuller

John Stephen Montrym

John Allen Tardif

Edward C Chen

Avi Bar-Zeev

Warren Fritz Kruger

J Andrew Goossen

Mark M Leather

Alexander Nankervis

Harjit Singh

Nicholas Robert Baker

Shahin Solki

Chi-Shung Wang

Charles Neill Boyd

Brian Etscheid

Craig C Peeper

Ashraf A Michail

Philippe Lacroute

Charles Neil Boyd

Douglas A Voorhies

Gordon Caruk

Michael Timothy Jones

Robert A Drebin

Zsolt Mathe

Xiaoling Xu

Shrijeet Mukherjee

Jeffrey Gongxian Cheng

Ning Xu

Kurt Barton Akeley

Thomas Edwin Frisinger

Matthew William Lee

Georg Klein

Alex Chalfin

Andrew Martin Pearson

James Andrew Goossen

Gregory C Buchner

Allison Klein

Joel D Wilke

Elaine Poon

Jeffrey Daudel

Jarrett Redd

Peter Ostrin

David Lloyd Morgan

Daniel M Gessel

Mark Witzel

Systems and methods for ray tracing acceleration structure level of detail processing are described. An example graphics processing system is to retrieve a first level of detail value for a sub-tree from a level of detail residency map corresponding to a bounding volume hierarchy of objects. The graphics processing system is to determine a second level of detail value for the sub-tree. The graphics processing system is to select a final level of detail value for the sub-tree based on a comparison between the first level of detail value for the sub-tree and the second level of detail value for the sub-tree. The graphics processing system is to, based on the final level of detail value for the sub-tree, select child nodes in an acceleration structure tree and trace the selected child nodes.

Systems and methods for ray tracing acceleration structure level of detail processing

Graphics processing systems and methods with geometry level of detail processing are described. An example graphics processing system includes a processor configured to retrieve a first level of detail value for a meshlet instance. The processor may further be configured to compute a second level of detail value for a meshlet instance. The processor may further be configured to, based on a comparison between the first level of detail value for the meshlet instance and the second level of detail value for the meshlet instance, select a final level of detail value for the meshlet instance. The processor may further be configured to fetch vertices and corresponding indices for the meshlet instance based on the final level of detail value for the meshlet instance and process the vertices of the meshlet instance.

Graphics processing systems and methods with geometry level of detail processing

Logically-defined pixel interfaces and video frame transfer techniques are provided herein. In one example, a method includes receiving a video frame representing source pixels, where the video frame comprises logical pixels that each represent more than one source pixel according to a selected sizing and metadata that indicates the selected sizing for the logical pixels and indicators of which pixels included in the video frame comprise the logical pixels. The method also includes interpreting the metadata for the logical pixels to map each of the logical pixels across more than one output pixel according to the selected sizing and the indicators included in the metadata.

Video frame interfaces for logically-defined pixels

Logic integrated with a memory and related methods for performing background functions are provided. A method in a memory includes, in response to a request from a host separate from the memory, initiating processing of a background function. The method further includes automatically monitoring the memory to detect whether any standard operation requiring a use of at least one of the plurality of the memory cells of the memory or at least one data path of the memory is being performed. The method further includes automatically suspending the processing of the background function when the standard operation requiring the use of a memory cell or a data path of the memory is detected unless the processing of the background function requires only resources that are provided as part of the logic integrated with the memory and that are configured to process only the background function.

Performing background functions using logic integrated with a memory

Methods and devices for rendering graphics in a computer system include a graphical processing unit (GPU) with a flexible, dynamic, application-directed mechanism for varying the rate at which fragment shading is performed for rendering an image to a display. In particular, the described aspects include determining, at a rasterization stage, map coordinates based on coarse scan converting a primitive of an object, the map coordinates indicating a location on a sampling rate parameter (SRP) map of a fragment within the primitive of the object, and identifying a lookup value for the fragment within the primitive of the object based at least on map coordinates, and calculating a respective fragment variable SRP value for the fragment within the primitive of the object based at least on the lookup value.

Variable rate shading

Variable pixel rate video output and display techniques for computing systems and user devices are presented herein. In one example, a method of providing video data for display on a display device includes determining logical pixels with variable sizing that each represent one or more source pixels comprising at least a portion of a video frame. The method also includes producing metadata describing the variable sizing for the logical pixels, and transferring the metadata with data representing the logical pixels over a display interface for display of at least the portion of the video frame on the display device that maps the logical pixels across target pixels of the display device.

Variable pixel rate display interfaces

Methods and devices for rendering graphics in a computer system include a graphical processing unit (GPU) with a flexible, dynamic, application-directed mechanism for varying the rate at which fragment shading is performed for rendering an image to a display. In particular, the described aspects allow different shading rates to be used for different regions of a primitive based on a new, interpolated shading rate parameter. In other words, the described aspects enable the GPU to change shading rates on-the-fly between different fragments of each primitive. Additionally, or independently, the GPU utilizes each respective shading rate parameter to determine how many sample positions to consider to be covered by the computed shaded output, e.g., the fragment color, thereby allowing the color sample to be shared across two or more pixels.

Methods and devices for performing variable rate shading are described. Invocation information and lineage information for each pixel of a plurality of pixels of a primitive are stored in an invocation buffer and a lineage buffer of a graphics processing unit. One or more deferred shading or post-processing operations are performed on the image based at least in part on the invocation information and the lineage information associated with each pixel of the plurality of pixels.

Tracking pixel lineage in variable rate shading

Embodiments of a peripheral component are described herein. Embodiments provide alternatives to the use of an external bridge integrated circuit (IC) architecture. For example, an embodiment multiplexes a peripheral bus such that multiple processors in one peripheral component can use one peripheral interface slot without requiring an external bridge IC. Embodiments are usable with known bus protocols.

Peripheral component

Systems, methods, apparatuses, and software for graphics processing systems in computing environments are provided herein. In one example, a method of handling tiled resources in graphics processing environments is presented. The method includes establishing, in a graphics processing unit, a residency map having values determined from memory residency properties of a texture resource, and sampling from the residency map at a specified location to determine a residency map sample for the texture resource at the specified location, where the residency map sample indicates at least an initial level of detail presently resident and a smoothing component to reach a next level of detail.

Texture residency hardware enhancements for graphics processors

Examples are disclosed that relate to depth-aware late-stage reprojection. One example provides a computing system configured to receive and store image data, receive a depth map for the image data, processing the depth map to obtain a blurred depth map, and based upon motion data, determine a translation to be made to the image data. Further, for each pixel, the computing system is configured to translate an original ray extending from an original virtual camera location to an original frame buffer location to a reprojected ray extending from a translated camera location to a reprojected frame buffer location, determine a location at which the reprojected ray intersects the blurred depth map, and sample a color of a pixel for display based upon a color corresponding to the location at which the reprojected ray intersects the blurred depth map.

Depth-aware reprojection

An internal bus architecture and method is described. Embodiments include a system with multiple bus endpoints coupled to a bus. In addition, the bus endpoints are directly coupled to each other. Embodiments are usable with known bus protocols.

Internal bus architecture and method in multi-processor systems

Growing community of inventors

Palo Alto, CA, United States of America

Mark Stefan Grossman