Sun Microsystems, Inc.

Advanced Micro Devices Corporation

F5 Networks, Inc.

Oracle America, Inc.

Mark S Young

Russell N Mirov

Michel P Cekleov

William M Baldwin

John Drew

Michael C Shebanow

Vineet Dujari

James Goodwin

David Zalatimo

Joseph Meza

Avner Ben-Dor

Michel Cekleov

Disclosed is a method and apparatus for crossbar arbitration. In one embodiment, the crossbar arbitration includes a memory, a plurality of functional units that transfer data to and from the memory, a crossbar unit that provides a data path from each unit to the memory, and an arbitration unit that monitors data traffic generated by each functional unit through the crossbar unit and assigns a priority to each functional unit based on the data traffic. In another embodiment, the crossbar arbitration includes a method for data transfer arbitration including monitoring data transfers for a plurality of devices, and assigning a priority to each device corresponding to the amount of data transfers generated by the device.

Arbitration and crossbar device and method

A system is described having a network, a bus and an interface coupling the network to the bus. A host is coupled to the network and executes software to generate packets for communication on the network. A bus device is coupled to the bus. The interface and host coordinate to transport bus device packets between the host and the bus device via tunneling over the network.

Tunneling between a bus and a network

A method is provided for controlling transitions between a first and second clock frequency signal in first and second components electrically coupled together and in communication with one another. The method comprises asserting a freeze signal to cause communications between the first and second components to cease. A freeze acknowledge signal is then received from the first and second components, indicating that communications therebetween have ceased. A change signal is delivered to the first and second components to cause the components to switch between the first and second clock frequency signals.

Method and apparatus for controlling transitions between a first and a second clock frequency

A method for operating a cache having a sleep mode is provided. The cache is located within a memory hierarchy of a computer system, and the method is comprised of receiving a first cache request, and servicing the first cache request. A sleep mode signal is asserted in response to completion of the servicing of the first cache request. Thereafter, a second cache request is received, and the sleep mode signal is deasserted in response to receiving the second cache request. Thereafter, the second cache request is serviced.

Method and apparatus for reducing power consumption in a cache memory system

A method for controlling thermal cycles in a computer system is provided. The method is comprised of receiving a request to transition the computer system from a first operating mode to a second operating mode, where less power is consumed in the second operating mode. A historical rate at which the computer system has transitioned between the first and second operating modes is determined, and the requested transition is permitted in response to the historical rate being less than a first preselected setpoint, but denied in response to the historical rate being greater than the first preselected setpoint.

Method and apparatus for reducing power consumption

A method for controlling operation of a bus and components coupled thereto is provided. The method is comprised of receiving a request for a bus transaction from one of the components coupled to the bus. Thereafter, the frequency of a clock signal supplied to at least the requesting component is increased, and the requested bus transaction is serviced. The frequency of the clock signal supplied to at least the requesting component is decreased upon completion of the requested bus transaction.

Method and apparatus for controlling a bus clock frequency in response to a signal from a requesting component

In one aspect of the present invention, a method for controlling the operation of a phase locked loop circuit is provided. The method is comprised of monitoring a frequency of a system clock, and a first signal is delivered in response to the detected frequency of the system clock being greater than a preselected setpoint. A second signal is delivered in response to the detected frequency of the system clock being less than a preselected setpoint. A first operating mode of the phase locked loop circuit is selected in response to receiving the first signal. The first mode of operation allows the phase locked loop circuit to synchronize with a clock signal in a first preselected range of frequencies. A second operating mode of the phase locked loop circuit is selected in response to receiving the second signal. The second mode of operation allows the phase locked loop circuit to synchronize with a clock signal in a second preselected range of frequencies.

A phase locked loop circuit is provided. The phase locked loop circuit is comprised of a first and second divide-by-N counter, a phase comparator, a voltage controlled oscillator, a clock tree, and a feedback path. The first divide-by-N counter is adapted to receive a first clock signal and provide a second clock signal. The phase comparator has a first and second input terminal and an output terminal. The phase comparator is adapted to compare the phase of signals applied to the first and second input terminals and deliver a signal at the output terminal having a magnitude indicative of a difference in the phases of the signals. The first input terminal is coupled to receive the second clock signal. The voltage controlled oscillator is coupled to receive the phase difference signal and deliver a third clock signal having a frequency responsive thereto. The second divide-by-N counter is coupled to receive the third clock signal and deliver a fourth clock signal. The clock tree is coupled to receive the third clock signal and deliver at least one fourth clock signal. The feedback path is coupled to deliver the fourth clock signal to the second input terminal of the phase comparator.

A memory system is provided. The memory system is comprised of a memory, a clock signal generator, a phase locked loop circuit, and a bypass circuit. The clock signal generator produces a first clock signal. The clock signal generator has a first mode of operation in which the first clock signal has a first frequency and a second mode of operation in which the first clock signal has a second frequency. The phase locked loop circuit is associated with the memory and adapted for receiving the first clock signal and providing a synchronized second clock signal to the memory. The bypass circuit is adapted to deliver the first clock signal to the memory in the second mode of operation.

A method is provided for operating an electronic device by monitoring operating characteristics of the electronic device, and determining from the monitored operating characteristics to operate at least a portion of components within the electronic device in a first, second, or third mode of operation. The first, second, and third modes of operation consume power at first, second, and third different rates. At least a portion of the components are instructed to switch between the first, second, and third modes.

A power supply is provided. The power supply is comprised of a first power module, a second power module, and a controller. The first power module is capable of delivering a first preselected amount of power. The second power module is capable of delivering a second preselected amount of power. The first and second power modules are coupled together to be capable of delivering an aggregate amount of power related to the first and second preselected amounts of power. The controller is adapted to selectively enable the first and second power modules to make power available in one of the first preselected amount, the second preselected amount, and the aggregate amount.

In a computer system comprising a CPU, a cache memory and a main memory wherein the cache memory is virtually addressed, and some of the virtual addresses are alias address to each other, a cache memory controller comprising a cache control logic, a cache tag array, a memory management unit, and an alias detection logic is provided. The cache control logic skips flushing of a cache line if the cache line is corresponding to a memory block in a non-cacheable physical memory page, thereby avoiding unnecessary flushes and allowing the CPU to update the cache memory and the main memory using an improved write through and no write allocate approach that reduces cache flushes.

Write through virtual cache memory, alias addressing, and cache flushes

A method and apparatus for generating a check sum and a syndrome for detecting errors in a series of bytes comprising a plurality of stages, each stage comprising a plurality of networks of exclusive OR gates, a memory and an exclusive OR gate for exclusively ORing the outputs of the networks resulting from a byte transmitted therethrough with the results stored in a memory in a previous stage due to a previous byte. Each of the stages and the networks therein correspond to a term in a Reed-Solomon polynomial. Except for differences in the number and construction of the networks in each stage, each of the stages are substantially identical and can be selectively used for detecting single and double burst errors.

Method and apparatus for error detection and correction in systems

A method and apparatus for transferring data between a disk and a CPU is disclosed comprising a pair of toggling header buffers and a pair of toggling data buffers. In operation, data is transferred between a sector on a disk and one of the data buffers under the control of one of the header buffers. While the data in the header buffer is being transferred between the data buffer and a CPU, data is transferred between an adjacent sector on the disk and the other data buffer under the control of the other header buffer. The rate of transfer of data between the data buffer and the CPU is higher than the rate of transfer of the data between the disk and the other data buffer. This provides sufficient time to check the data transferred from and to the CPU for errors and to address a new sector on the disk prior to the completion of the data transfer of the previous sector between the disk and the data buffer. By means of the method and apparatus disclosed, all sectors in a track on a disk can be transferred between a disk and a CPU within a single revolution of the disk.

Method and apparatus for transferring data between a disk and a central

A method and apparatus for reading data from a disk having missing or unreadable field address marks. Expected address marks are searched for within a time window which is generated using a counter. When an expected address mark is generated at any time within the time window, the counter is set or reset to generate another time window within which the next address mark is expected to occur. By starting or restarting the counter each time an expected address mark is detected the effects of variations in spindle speed which occur prior to the detection of the address mark are eliminated, thus increasing the probability that readable address marks will be detected within a time window.

Growing community of inventors

Mountain View, CA, United States of America

Mark S Young