Tandem Computers Incorporated

Other

Compaq Computer Corporation, Inc.

Array Technology, LLC

Mark S Walker

Albert S Lui

William A Brant

David C Stallmo

William T Fuller

Wing Ming Chan

Mary Ann Walker

Srikumar R Chandran

Edward J Rhodes

Harald W Sammer

Strikumar R Chandran

A system for drying structures including an enclosed housing with a plurality of outlet openings, a plurality of flexible outlet hoses each connected to a respective outlet opening, and a vacuum motor engaged with the housing such that an outlet of the vacuum motor is exhausted into an interior of the housing so as to pressurize the interior of the housing such that compressed air is directed through the plurality of outlet hoses. Also a method of drying an interior of a structure, including placing a pressurized drying system adjacent a region of a structure, forming a plurality of openings in surfaces of the structure where the surfaces define enclosed spaces, inserting distal ends of outlet hoses of the pressurized drying system into respective openings of the surfaces of the structure, and engaging the pressurized drying system so as to generate a flow of pressurized air and to direct the pressurized air into the enclosed spaces.

Pressurized drying system

A system for moving fluid from one location to another. The system comprising a fluid delivery system, a first piece of flexible tubing that receives fluid from the fluid delivery system and a second piece of flexible tubing. The system further includes a connector having an aperture that receives the second piece of flexible tubing. The connector is then positioned inside the first piece of flexible tubing so that the connector is urged against the inner walls of the first piece of flexible tubing so that fluid can be communicated from the first piece of flexible tubing to the second piece of flexible tubing.

Connector for use with inflatable tubing

A highly reliable computer memory storage system that is divided into subsystems, each of which is provided in triplicate: a primary subsystem, a backup subsystem and a spare subsystem. Upon detection of a non-recoverable failure in a primary subsystem, the backup subsystem substantially immediately assumes the tasks of the primary subsystem while the spare subsystem is integrated into the operation of the computer memory storage system. The triple replication of all subsystems and mechanisms for detecting failures in at least the primary and secondary subsystems provides an overall memory system which is highly reliable and substantially never requires servicing. In an alternative embodiment, three subsystems can share a load equally, for example a cooling or power supply load requirement. Upon failure, of any one or two of such three redundant subsystems, the remaining subsystems(s) is built with sufficient extra capacity that remaining subsystem(s) can still supply the total power or cooling requirements of the system.

Continuously available computer memory systems

A system and method for ensuring the completion and integrity of data modification operations to a redundant array data storage system and for ensuring the integrity of redundancy values in such a system. The system combines four elements: reliable host processing provided by primary and secondary CPU's with check pointing of operations, so that the secondary CPU can complete initiation of a data modification operation if the primary CPU fails; block-buffering of Write data in a host CPU adapter before transmission of the data to a RAID array controller, so that failure of the host CPU after buffering completes does not interfere with completion of the data modification operation; reliable array processing provided by primary and secondary array controllers with check pointing of operations, so that the secondary array controller can complete a data modification operation if the primary array controller fails; and battery-backup for the power supply to the array controller and the storage units comprising the storage array, or, in the alternative, non-volatile memory in the array controller sufficient to store all data modification operation command information for data records that have not been successfully written to the storage units, for use in subsequent retries.

System and method for ensuring write data integrity in a redundant array

A fault-tolerant storage device array using a copyback cache storage unit for temporary storage. When a Write occurs to the RAID system, the data is immediately written to the first available location in the copyback cache storage unit. Upon completion of the Write to the copyback cache storage unit, the host CPU is immediately informed that the Write was successful. Thereafter, further storage unit accesses by the CPU can continue without waiting for an error-correction block update for the data just written. In a first embodiment of the invention, during idle time for relevant storage units of the storage system, an error-correction block is computed for each 'pending' data block on the copyback cache storage unit, and the data block and corresponding error-correction block are copied to their proper location in the RAID system. The copyback cache storage unit in effect stores 'peak load' Write data and then completes the actual Write operations to the RAID system during relatively quiescent periods of I/O accesses by the CPU. In a second embodiment of the invention, after Write data is logged to the copyback cache storage unit, normal Read-Modify-Write operation by the RAID system controller continues in overlapped fashion with other CPU I/O accesses using Write data in the controller's buffer memory. Performance is enhanced because the CPU can continue processing as soon as the simple Write operation to the copyback cache storage unit completes, thus eliminating the delay caused by a normal Read-Modify-Wrote RAID system. In this embodiment, the copyback cache storage unit acts more as a running 'log' of Write data.

Storage device array architecture with copyback cache

A multiprocessing computer system with data storage array systems allowing for linear and orthogonal expansion of data storage capacity and bandwidth by means of a switching network coupled between the data storage array systems and the multiple processors. The switching network provides the ability for any CPU to be directly coupled to any data storage array. By using the switching network to couple multiple CPU's to multiple data storage array systems, the computer system can be configured to optimally match the I/O bandwidth of the data storage array systems to the I/O performance of the CPU's.

Linear and orthogonal expansion of array storage in multiprocessor

The present invention is an input/output controller for providing total data integrity for any single point failure. The I/O controller comprises a processor module having two microprocessors, an associated memory, a direct memory access module ('DMA'), and a processor support module ('PSM'); a device drive interface; and a channel interface. The two microprocessors are operated in lockstep as a dual modular redundant processor system. The processors provide true and complement, respectively, addresses, data and control strobes. The PSM compares the true and complement data to detect errors (i.e., corresponding data bits not being a true-complement pair) and generates parity protected data (and checks parity) on the data bus. The PSM also generates and checks dual railed control strobes and provides synchronization of all control strobes and interrupt signals to enable the tru-complement pair of microprocessors to operate in lockstep. The DMA compares the redundant addresses from the processors to detect errors and to generate parity protected addresses (and check parity) on the address bus. The DMA also generates the checks bus arbitration signals and controls direct memory access. Self-checking checkers are used to check the various dual railed, true-complement pairs of signals to detect, locate and isolate internal faults. Mis-compares between true-complement address, data and control signals and parity errors detected in reading program instructions from memory all are treated as fatal errors, which cause both processors to halt. Other types of errors are treated as nonfatal, which cause processor exceptions during which appropriate programming is executed to locate and isolate such errors.

High level self-checking intelligent I/O controller

A digital logic circuit and method for synchronizing the leading edges skewed true-complement signal pair. The circuit is comprised of two similar, interconnected circuit halves, each of which includes three D flip-flop stages. The outputs from the second D flip-flop stages from the two circuit halves are applied to the two inputs of two identical logic gates, such that the signal pair is synchronously transmitted to a pair of output gates through a third D flip-flop stage in each circuit half. The second D flip-flop stages also prevent metastable states from reaching the synchronizer output. Metastable states may result if the input setup time is violated for the first D flip-flop stages. The third D flip-flop stage in each circuit half also eliminates any signal irregularities generated in the logic circuitry from appearing on the synchronizer output lines. The circuit is self-checking in that any single fault in the input signals or in the synchronizer circuit itself will result in the synchronizer output pair not having a true complement relationship.

Growing community of inventors

Los Gatos, CA, United States of America

Mark S Walker