Cirrus Logic Inc.

Silicon Laboratories Inc.

Mark S Spurbeck

Richard T Behrens

Li Du

Jeffrey William Scott

William G Bliss

Donald A Kerth

G Tyson Tuttle

Vishnu Shankar Srinivasan

G Diwakar Vishakhadatta

German S Feyh

Tod Paulus

Trent O Dudley

David R Welland

David E Reed

Howard H Sheerin

A radio-frequency (RF) receiver includes a receiver analog circuitry and a receiver digital circuitry. The receiver analog circuitry resides within a first integrated circuit and the receiver digital circuitry resides within a second integrated circuit. The second integrated circuit couples to the first integrated circuit via a one-bit digital interface. The receiver analog circuitry receives an RF signal and processes the received RF signal to generate a digital signal. The receiver analog circuitry provides the digital signal to the receiver digital circuitry. The receiver digital circuitry includes a digital down-converter circuitry that mixes the digital signal with an intermediate frequency (IF) local oscillator (LO) signal to generate a digital down-converted signal. The receiver digital circuitry also includes a digital filter circuitry that filters the digital down-converted signal to generate a filtered digital signal.

Digital architecture for radio-frequency apparatus and associated methods

A radio-frequency (RF) receiver includes a receiver analog circuitry and a receiver digital circuitry coupled together. The receiver analog circuitry receives an RF signal. The receiver analog circuitry processes the received RF signal and generates a digital signal that it provides to the receiver digital circuitry. The receiver digital circuitry includes a digital down-converter circuitry that mixes the digital signal provided by a receiver analog circuitry with a digital intermediate frequency (IF) local oscillator signal to generate a digital down-converted signal. The receiver digital circuitry also includes a digital filter circuitry that filters the digital down-converted signal to generate a filtered digital signal. The digital filter circuitry provides a notch at a frequency that corresponds to a residual DC offset of the receiver analog circuitry.

Notch filter for DC offset reduction in radio-frequency apparatus and associated methods

A sampled amplitude read channel for magnetic disk recording which asynchronously samples the analog read signal, adaptively equalizes the resulting discrete time sample values according to a target partial response, extracts synchronous sample values through interpolated timing recovery, and detects digital data from the synchronous sample values using a Viterbi sequence detector is disclosed. To minimize interference from the timing and gain control loops, the phase and magnitude response of the adaptive equalizer filter are constrained at a predetermined frequency using an optimal orthogonal projection operation as a modification to a least mean square (LMS) adaptation algorithm. Further, with interpolated timing recovery, the equalizer filter and its associated latency are removed from the timing recovery loop, thereby allowing a higher order discrete time filter and a lower order analog filter.

Adaptive equalization and interpolated timing recovery in a sampled amplitude read channel for magnetic recording

The invention includes disk drive circuitry, systems, and methods. The disk drive system comprises control circuitry and a disk device. The disk device stores data and transfers an analog signal representing the data. The control circuitry receives the analog signal, converts the analog signal into a digital signal, and transfers the digital signal. The control circuitry includes zero forcing circuitry and an adaptive filter. The zero forcing circuitry produces new coefficients for the adaptive filter. The control circuitry may also include an analog-to-digital converter, detector, decoder, and LMS circuitry. The analog-to-digital converter receives and samples the analog signal to generate a sampled signal. The adaptive filter shapes the sampled signal based on coefficients to produce an equalized signal. The detector detects binary data from the equalized signal, and the decoder decodes the binary data to generate the digital signal. Either the zero forcing circuitry or the LMS circuitry may be selected to produce the coefficient signal that adjusts the coefficients in the adaptive filter.

Zero forcing adaptive equalization in a disk drive read channel

The invention includes disk drive circuitry, systems, and methods. The disk drive system comprises control circuitry and a disk device. The disk device stores data and transfers an analog signal representing the data. The control circuitry receives the analog signal, converts the analog signal into a digital signal, transfers the digital signal, and biases an error signal. The control circuitry includes an analog-to-digital converter, adaptive filter, a decoder, and error signal circuitry. The analog-to-digital converter receives and samples the analog signal to generate a sampled signal. The adaptive filter shapes the sampled signal based on coefficients to produce a shaped signal. The decoder decodes the shaped signal to generate the digital signal. The error signal circuitry generates the biased error signal to adjust the coefficients in the adaptive filter. The error signal circuitry may generate the error signal by determining a difference between the shaped signal from the adaptive filter and an ideal signal. The error signal circuitry may bias the error signal by biasing the ideal signal. The error signal circuitry may bias the ideal signal by adjusting a slicer output by a step value.

Error signal biasing for an adaptive filter in a disk drive read channel

Gain and phase constrained adaptive equalizing filter in a sampled amplitude read channel for magnetic recording

Gain and phase constrained adaptive equalizing filter in a sampled

A sampled amplitude read channel for reading information stored on a magnetic medium by detecting digital data from a sequence of discrete time interpolated sample values, the interpolated sample values generated by interpolating a sequence of discrete time channel sample values generated by sampling pulses in an analog read signal from a magnetic read head positioned over the magnetic medium. A write VFO generates a write clock for writing digital data to the magnetic medium at a predetermined baud rate for a selected zone, and upon read back, the write VFO generates a sampling clock at a frequency slightly higher than the write frequency. A sampling device samples the analog read signal at the sampling clock rate to generate a sequence of discrete time channel samples that are not synchronized to the baud rate. The channel samples are equalized by a discrete time equalizing filter according to a predetermined partial response (PR4, EPR4, EEPR4, etc.). An interpolating timing recovery circuit, responsive to the equalized channel samples, computes an interpolation interval .tau. and, in response thereto, generates interpolated sample values substantially synchronized to the baud rate. The timing recovery circuit also generates a data clock for clocking a discrete time sequence detector for detecting the digital data from the interpolated sample values.

Sampled amplitude read channel employing interpolated timing recovery

A sampled amplitude read channel is disclosed for disk storage systems which asynchronously samples an analog read signal, adaptively equalizes the resulting discrete time sample values according to a target partial response, extracts synchronous sample values through interpolated timing recovery, and detects digital data from the synchronous sample values using a Viterbi sequence detector. To increase the speed of the read channel, the FIR filters in the equalizer and interpolator are implemented according to a residue number system. Further, the residue number system implementation of the FIR filters uses 'one-hot' encoding to decrease power dissipation.

Sampled amplitude read channel employing a residue number system FIR

A sampled amplitude read channel reads user data and embedded servo data stored on a magnetic medium by detecting digital data from a sequence of discrete time interpolated sample values. A write frequency synthesizer generates a write clock for writing digital data to the magnetic medium at a predetermined baud rate for a selected zone, and upon read back, a read frequency synthesizer generates a fixed sampling clock at a frequency slightly higher than the write frequency at the outer zone. A sampling device samples the analog read signal at this fixed sampling rate across the data zones and servo wedges to generate a sequence of discrete time channel samples that are not synchronized to the baud rate. Before sampling, an analog receive filter processes the read signal to attenuate aliasing noise without having to adjust its spectrum across data zones or servo wedges. A discrete time equalizing filter equalizes the channel samples according to a predetermined partial response (PR4, EPR4, EEPR4, etc.). An interpolating timing recovery circuit, responsive to the equalized channel samples, computes an interpolation interval .tau. and, in response thereto, generates interpolated sample values substantially synchronized to the baud rate. The timing recovery circuit also generates a synchronous data clock for clocking a discrete time sequence detector and pulse detector which detect the digital user and servo data from the interpolated sample values.

Fixed sample rate sampled amplitude read channel for zoned magnetic

A sampled amplitude read channel reads information stored on a magnetic medium by detecting digital data from a sequence of discrete time interpolated sample values, the interpolated sample values generated by interpolating a sequence of discrete time channel sample values generated by sampling pulses in an analog read signal from a magnetic read head positioned over the magnetic medium. A write VFO generates a write clock for writing digital data to the magnetic medium at a predetermined baud rate for a selected zone, and upon read back, the write VFO generates a sampling clock at a frequency slightly higher than the write frequency. A sampling device samples the analog read signal at the sampling clock rate to generate a sequence of discrete time channel samples that are not synchronized to the baud rate, and the channel samples are equalized by a discrete time equalizing filter according to a predetermined partial response (PR4, EPR4, EEPR4, etc.). An interpolating timing recovery circuit, responsive to the equalized channel samples, computes an interpolation interval .tau. and, in response thereto, generates interpolated sample values substantially synchronized to the baud rate. The timing recovery circuit also generates a data clock for clocking a discrete time sequence detector which detects the digital data from the interpolated sample values. In a cost reduced implementation, the interpolation filter coefficients are computed in real time as a function of the interpolation interval .tau..

Cost reduced interpolated timing recovery in a sampled amplitude read

A method and apparatus for computing, in real time, the coefficients C.sub..tau. (n) of a time varying FIR filter according to an optimum singular value decomposition (SVD) algorithm. The coefficients of a plurality of FIR filters are represented by a M.times.N matrix A.sub.M.times.N, where M is the number of FIR filters and N is the number of coefficients in the impulse response of each FIR filter (i.e., the number of filter taps). The A.sub.M.times.N matrix is factored into F.sub.M.times.N and G.sub.N.times.N matrices, and a singular value decomposition of the A.sub.M.times.N matrix is computed as A.sub.M.times.N =U.sub.M.times.N .cndot.D.sub.N.times.N .cndot.V.sub.N.times.N, where U.sub.M.times.N is a M.times.N unitary matrix, D.sub.N.times.N is a N.times.N diagonal matrix {.sigma..sub.1, .sigma..sub.2, . . . , .sigma..sub.N }, .sigma..sub.i are the singular values of A.sub.M.times.N (and .sigma..sub.1 .gtoreq..sigma..sub.2 . . . .gtoreq..sigma..sub.N .gtoreq.0), and V.sub.N.times.N is a N.times.N unitary matrix. By selecting a predetermined L number of the largest singular values .sigma. to generate a reduced size diagonal matrix D.sub.L.times.L, it is possible to extract the first L columns from the U.sub.M.times.N matrix to form a reduced U.sub.M.times.L matrix and to extract the first L rows from the V.sub.N.times.N matrix to form a reduced V.sub.L.times.N matrix. In this manner the filter matrix A.sub.M.times.N can be approximated by reducing the F.sub.M.times.N and G.sub.N.times.N matrices by replacing N with L such that:

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Louisville, CO, United States of America

Mark S Spurbeck