Motorola Corporation

Mark S Roberton

Edward Outlaw Travis, Jr

Ruiqi Tian

Tat-Kwan Edgar Yu

Aykut Dengi

Sejal N Chheda

Alfred J Reich

Robert Elliott Boone

Selective placement of polishing dummy feature patterns, rather than indiscriminate placement of polishing dummy feature patterns, is used. Both low frequency (hundreds of microns and larger) and high frequency (10 microns and less) of topography changes are examined. The polishing dummy feature patterns can be specifically tailored to a semiconductor device and polishing conditions used in forming the semiconductor device. When designing an integrated circuit, polishing effects for the active features can be predicted. After polishing dummy feature pattern(s) are placed into the layout, the planarity can be examined on a local level (a portion but not all of the device) and a more global level (all of the device, devices corresponding to a reticle field, or even an entire wafer).

Method for adding features to a design layout and process for designing a mask

Semiconductor device and a process for designing a mask

Growing community of inventors

Los Angeles, CA, United States of America

Mark S Roberton