Synopsys, Inc.

Quickturn Design Systems, Inc.

Mark S Papamarcos

Andrew J Read

Robert K Mardjuki

Peter R Jaeger

Robert K Couch

Wayne P Heideman

Lawrence C Widdoes, Jr

William F Kappauf

Ingo Schaefer

John E Chilton

Tony R Sarno

Melvin Rudin

Norman Francis Kelly

Louis K Scheffer

Curt Blanding

Michael C Tsou

Bernard Y Chan

An improved system or and method of connecting a hardware modeling element to the pin electronics circuitry of a hardware modeling system, with the improved system having circuitry and structures that will allow it to be connected to a hardware modeling system that is powered, circuitry to indicate to the pin electronics circuitry that the improved system is connected to it, circuitry to identify the hardware modeling element supported by the improved system to the hardware modeling system, circuitry to indicate to the hardware modeling system when the hardware modeling element is initialized so evaluation of it by the hardware modeling system can commence, circuitry to generate selectable supply voltages for the powering the hardware modeling element, and a hardware modeling element connector that will allow the connection of a family of hardware modeling elements to the same connector without the need to change the connector.

System for and method of connecting a hardware modeling element to a

A logic analysis subsystem in a time-sliced emulator. The logic analysis subsystem 'reconstructs' signals that were previously reduced by the compiler and allows the user to set breakpoints and triggers using these and other signals of the emulated circuit. The present invention includes a 'logic analysis subsystem compiler' and 'logic analysis subsystem hardware.' The logic analysis subsystem compiler is either a subpart of the regular emulator compiler or is a standalone compiler. It compiles the design to be emulated and generates control instructions for the logic analysis subsystem hardware. The logic analysis subsystem hardware is incorporated into the time-sliced emulator to receive signals generated by the emulator during emulation. When the logic analysis subsystem operates, the control instructions cause the logic analysis subsystem to reconstruct previously reduced signals received from the emulator. These signals (along with the signals received from the emulator) may be used by the user to set breakpoints and triggers in the logic analysis subsystem.

Logic analysis subsystem in a time-sliced emulator

A time-sliced hardware-based emulator including at least one of: programmable I/O assignment; programmable levels of DC voltage; programmable pull-up or pull-down resistors in the emulator on a pin-by pin basis; programmable forcing and/or disabling of value output from the emulator on each pin; programmable clocking; and programmable sample modes. An emulator is connected to a target system via a Pod System Interface (PSI), a specially designed cable, and a Pod User Interface (PUI). For data traveling from the emulator to the target system, each PSI receives up to 128 bits of data from the emulator. The cable, however, is only 32 bits wide. Therefore, the emulator multiplexes the data sent over the cable, sending eight interleaved groups of 32 bits to the PSI in accordance with a fast clock signal. Each PUI receives the groups of 32 bits from the PSI and sends them to the target system in accordance with control signals from the emulator. For data traveling from the target system to the emulator, each PUI receives up to 128 bits of data from the target system. Each PUI sends four groups of 32 bits in accordance with a fast clock signal. Each PSI receives the groups of 32 bits and holds them in an internal register, sending the received bits to the emulator under control of the emulator.

Software reconfigurable target I/O in a circuit emulation system

An improved hardware modeling system that is preferably embodied as a stand-alone system for networked connection to one or a variety of host computers that are used to design digital electronics systems, the hardware modeling system having a network interface for communicating between the hardware modeling system and the host computer, a central processing unit for controlling operation of the hardware modeling system, a central timing unit for generating timing signals for use in the operation of the hardware modeling system including the generation of precision clocks, data formatting strobes and sample strobes, an internal pattern bus for transmission of read/write requests from the central processing unit in one operational mode and pattern sequences for stimulation of the hardware modeling element in a second operational mode, a pattern controller for controlling presentation and delivery of the pattern sequences to the pattern bus, a pattern memory connected to the pattern controller for storing stimulus pattern sequences, pin electronics circuitry which is used for driving the pattern sequences on the pattern bus to the hardware modeling element and then sensing the five state values of the hardware modeling element pins, and an adapter that is used for fixturing the hardware modeling element to the pin electronics circuitry with the adapter supporting live insertion into a powered hardware modeling system.

Hardware modeling system and method of use

An improved system for and method of connecting a hardware modeling element to the pin electronics circuitry of a hardware modeling system, with the improved system having circuitry and structures that will allow it to be connected to a hardware modeling system that is powered, circuitry to indicate to the pin electronics circuitry that the improved system is connected to it, circuitry to identify the hardware modeling element supported by the improved system to the hardware modeling system, circuitry to indicate to the hardware modeling system when the hardware modeling element is initialized so evaluation of it by the hardware modeling system can commence, circuitry to generate selectable supply voltages for the powering the hardware modeling element, and a hardware modeling element connector that will allow the connection of a family of hardware modeling elements to the same connector without the need to change the connector.

Growing community of inventors

San Jose, CA, United States of America

Mark S Papamarcos