Intel Corporation

Fujitsu Siemens Computers Gmbh

Siemens Pyramid Information Systems, Inc.

Siemens Ak.

Mark S Myers

Mahesh U Wagh

Stephen R Van Doren

David B Johnson

Marc Alan Quattromani

Debendra Das Sharma

Michelle C Jen

Dimitrios Ziakas

Bassam N Coury

Ramacharan Sundararaman

Sunil R Shenoy

Don Soltis

Eileen Riggs

M Vittal Kini

Jeffery L Moll

Francesc Guim Bernat

Murugasamy K Nachimuthu

Susanne M Balle

Suraj Prabhakaran

Daniel Rivas Barragan

Slawomir Putyrski

Robert C Duzett

David L Budde

John Chun Kwok Leung

Jason Lewis

Ronald J Ebersole

Atiq A Bajwa

John Lynch

Stacey Lloyd

Paul Kayfes

Gerhard Bier

Stanley Kenoyer

Kent Mason

Charles Sealey

Sven Nilsson

Embodiments may be generally direct to apparatuses, systems, method, and techniques to provide multi-interconnect protocol communication. In an embodiment, an apparatus for providing multi-interconnect protocol communication may include a component comprising at least one connector operative to connect the component to at least one off-package device via a standard interconnect protocol, and logic, at least a portion of the logic comprised in hardware, the logic to determine data to be communicated via a multi-interconnect protocol, provide the data to a multi-protocol multiplexer to determine a route for the data, route the data on-package responsive to the multi-protocol multiplexer indicating a multi-interconnect on-package mode, and route the data off-package via the at least one connector responsive to the multi-protocol multiplexer indicating a multi-interconnect off-package mode. Other embodiments are described.

Techniques to support multiple protocols between computer system interconnects

Embodiments may be generally direct to apparatuses, systems, method, and techniques to determine a configuration for a plurality of connectors, the configuration to associate a first interconnect protocol with a first subset of the plurality of connectors and a second interconnect protocol with a second subset of the plurality of connectors, the first interconnect protocol and the second interconnect protocol are different interconnect protocols and each comprising one of a serial link protocol, a coherent link protocol, and an accelerator link protocol, cause processing of data for communication via the first subset of the plurality of connectors in accordance with the first interconnect protocol, and cause processing of data for communication via the second subset of the plurality of connector in accordance with the second interconnect protocol.

Techniques to support multiple interconnect protocols for a common set of interconnect connectors

Techniques for migration for composite nodes in software-defined infrastructures (SDI) are described. A SDI system may include a SDI manager component, including one or more processor circuits, configured to access one or more remote resources, the SDI manager component may include a partition manager configured to receive a request to create a composite node from an orchestrator component, the request including at least one preferred compute sled type and at least one alternative compute sled type. The SDI manager may create a composite node using a first compute sled matching the at least one alternative compute sled type. The SDI manager may determine, based upon a migration table stored on a non-transitory computer-readable storage medium that a second compute sled matching the at least one preferred compute sled type is available. The SDI manager may perform an migration from the first compute sled to the second compute sled. Other embodiments are described and claimed.

Methods and apparatus for SDI support for automatic and transparent migration

A high-performance, high-reliable backplane bus has a simple configuration and operation. An error reporting network (ERN) provides an inexpensive approach to collecting the error state of a whole system in a uniform and consistent way. The uniformity allows for simpler interface software and for standardized hardware handling of classes of errors. In a preferred embodiment, serial error registers are used, minimizing implementation cost and making the software interface to the serial registers much easier. Serial error information is transferred over a separate data path from the main parallel bus, decreasing the chance of the original error corrupting the error information. Each CPU is provided with a local copy of the entire body of error information. The redundancy minimizes the impact of a possible CPU failure and allows the CPUs to coordinate error recovery.

Error reporting network in multiprocessor computer

An interface circuit for interfacing one or more compute nodes to a mesh and for serving a wide range of MPP systems and a method for exchanging data between a first agent on an expansion bus and a second agent on a system bus through a bus bridge so as to maintain cache coherency with data cached by one or more agents on the system bus. Transaction requests are queued within the bus bridge, transactions are snooped on the system bus, and a record of pending transaction addresses is maintained. Issuance of a queued transaction having the same cache line address as a pending transaction is stalled until the pending transaction has been completed.

Compute node to mesh interface for highly scalable parallel processing system and method of exchanging data

In a massively parallel processing (MPP) system, bandwidth efficiency and message packet latency rates are improved by providing routing elements that detect, isolate and identify various routing errors. More specifically, system lock-up, caused by corrupted message packets, can be prevented by analyzing a given sequence of message packet codes and words as they are received by an input buffer associated with a routing element. By analyzing the sequence, it is possible to determine whether a tail code fails to arrive in the prescribed sequence. If a tail code has been received in a way that is inconsistent with an expected sequence, all of the message packet codes and words received at the buffer can be discarded until a valid message packet start code is received.

Torus routing element error handling and self-clearing with missing or extraneous control code feature

In a massively parallel processing (MPP) system, bandwidth efficiency and message packet latency rates are improved by providing routing elements that detect, isolate and identify various routing errors. More specifically, during the transmission of a message packet from a first routing element to a second routing element in the MPP system, link lock-up can be prevented effectively by determining whether the message packet contains a certain predefined quantity of data. Control codes, used for establishing the end to the message packet, can then be inserted into the message packet if it is determined that the message packet does, in fact, contain the predefined quantity of data.

TORUS routing element error handling and self-clearing with link lockup

In a massively parallel processing (MPP) system, data transmission between a first routing element to a buffer in a second routing element can be controlled more efficiently by generating a high and low watermark for the buffer, wherein the watermark values are based on a period of time required to transmit data between the routing elements. The amount of data stored in the buffer is then continuously compared to the high watermark value, and if the amount of data in the buffer is greater than or equal to the high watermark value, the first routing element becomes blocked from transmitting additional data to the buffer in the second routing element.

TORUS routing element error handling and self-clearing with programmable

Apparatus for queuing requests and replies on a pipelined packet bus. A RAM (212) buffers bus requests by storing packet information corresponding to each request to be sent over said bus in bus time slots allotted to each request. Three send slots (208) keep track of the state of three send requests that are stored in the RAM (212). Three receive slots (210) keep track of the state of three receive requests that are stored in the RAM (212). Nine send queue counters (230) are stepped through a series of states to track an outgoing request and to track a corresponding incoming reply. Six receive queue counters (232) are stepped through a series of states to track an incoming request and to track a corresponding reply. An output MUX (214) connected to the send and receive queues generates status information as to the state of the slots. The status information as to the state of the send and receive slots is used to control the incrementing or decrementing of the send queue counters (230) and the receive queue counters (232 ) in accordance with a predetermined system bus protocol.

Apparatus with a single memory and a plurality of queue counters for

A data processor bus in which information is transferred between agents attached to the bus by issuing request packets that request data from an agent on the bus and reply packets that return data requested by a request packet. A control method mixes request-and-reply packets on the bus by determining the use of a next-bus cycle using arbitration, reply deferral, and specification lines and the state of a grant queue and a pipe queue in accordance with a specified protocol. A request is forced to take the next available bus cycle upon the condition that there is an agent identified in the great queue and the pipeline queue is not full. A reply packet is forced to take the next available bus cycle upon the condition that the pipeline queue is full. A reply packet is forced to take the next available bus cycle upon the condition that the grant queue is empty and the pipeline queue is not empty. Giving requests precedence over replies to allows the pipeline to be kept as full as possible. A replying agent assigned to the highest priority slot 1 in the pipeline queue is allowed to defer its own slot in the pipeline queue until a later time to thereby permit a transaction in Slot 2 of the pipeline queue to be completed before the one ahead of it.

Method of increasing the bandwidth of a packet bus by reordering reply

An integrated circuit module (200) in which an error detection circuit (234, 263) compares data (204) generated internally on module (200) with data (108) generated externally from another substantially identical module (100). An error detect output (238) is asserted upon the condition that data (204) generated internally on module (200) and data (108) generated externally from module (100) do not match. A circuit (222, 224) alters the internally generated data (204) by injecting erroneous data into the internally generated data (204) to thereby generate altered data (230). Error anticipation control logic (210) generates a test condition (214, 216), which corresponds to the expected error condition caused by altered data. Comparison circuit (242) compares the actual error detect output (238, 240) with expected error detect output (214, 215). An error output (244) is asserted if the actual error detect output (238, 240) and the expected error detect output (214, 216) do not match.

Apparatus for self checking of functional redundancy check (FRC) logic

A functional-redundancy checking logic for checking identical chips whose outputs are time-variant programmable. Window logic (40, 60) on each chip creates a window associated with each programmed transition, set pulse (14) and reset pulse (15). For the set pulse (14), on the rising edge (42) of the window, an error flip-flop (50) is set. The flip-flop is merely set at this time; an error is not flagged. The window remains open for a fixed time period. During the time period that the window is open, if the output pin (24) is ever correctly asserted, then the flip-flop (50) is reset, thus clearing the error flag. However, if the pin (24) always remains incorrectly asserted, indicating an error, then the error flip-flop (50) remains set. When the window closes on the falling edge (46) of the window pulse, an error report pulse is created via the AND (52). The value on the flip-flop (50) at this time is reported as an error (54). An identical circuit checks the programmable reset pulse ( 15).

Methods and circuits for checking integrated circuit chips having

An error-checking system in which two substantially identical modules are checked by comparing the outputs (43, 63) from the chip logic (41, 61) on each modules with each other. One module is designated a master and the other module is designated a checker. The compare logic (46 or 66) is functional only when the module that it is on is designated as the checker. A control bit designates a module as either a master or a checker. A second control bit indicates when in a first state, that a module designated as a master drives the bus, and when in a second state that a module designated as a master and a module designated as a checker alternately drive the bus. Circuitry distinguishes a warm initialization from a cold initialization. A bit in a register causes a module designated as a master to become a checker upon every alternate warm initialization, so that the module alternates between being a master and a checker only each time a warm initialization occurs.

Apparatus for on-line checking and reconfiguration of integrated circuit

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Portland, OR, United States of America

Mark S Myers