Intel Corporation

International Business Machines Corporation

Mark S Milshtein

Terry I Chappell

Thomas D Fletcher

Milo D Sprague

Sang Hoo Dhong

Gerhard Schrom

Jeremy H Burroughes

Steven Lorenz Wright

Sandip Tiwari

Barbara A Chappell

Alexander Lyakhov

Michael A Tischler

Mark B Ritter

Michael Kevin Ciraula

Rudolf Adriaan Haring

Dennis L Rogers

Sudhir Muniswamy Gowda

Talal K Jaber

Ravi S Ananth

Edward Seewann

Kevin (Xia) Dai

Max Eduardo De Ycaza

Pho Hoang Nguyen

Described is an apparatus which comprises: a low-side switch coupled to an output node for providing regulated voltage supply; and a first driver operable to cause the low-side switch to turn off when the output node rises above a first transistor threshold voltage. Described is also a voltage regulator which comprises: a signal generator to generate a pulse-width modulated (PWM) signal; a bridge having a low-side switch coupled to an output node for providing regulated voltage supply according to the PWM signal; a first driver operable to cause the low-side switch to turn off when the output node rises above a first transistor threshold voltage; and a bridge controller to provide control signals to the first driver. The voltage regulator may operate without diode clamps and its operation is self-timed. The voltage regulator also provides tolerance against process variation.

Bridge driver for a switching voltage regulator which is operable to soft-switch and hard-switch

A global clock self-timed circuit initiates a precharge pulse in response to which a domino node is precharged. A self-terminating precharge circuit coupled to the global clock self-timed circuit and the domino node terminates the precharge pulse after the domino node has been precharged.

Global clock self-timed circuit with self-terminating precharge for high frequency applications

A dynamic incrementer, implemented in the Self Resetting Complementary Metal Oxide Semiconductor (SRCMOS) circuit family, which internally performs single rail calculations and which generates the dual rail result using a strobing technique. The carry-lookahead function is implemented with an OR tree using the complement input signals, resulting in a very fast and economical incrementer.

High performance, low power incrementer for dynamic circuits

A method is provided for precharging a node in an integrated circuit in which the node is precharged a first predetermined delay after the node evaluates and, thereafter, the precharge ceases after a second shorter predetermined delay.

Two legged reset controller for domino circuit

A variable width pulse generator. The pulse generator includes a pulse circuit responsive to a reset signal to provide a pulse circuit signal. A variable delay reset loop path, coupled to the pulse circuit, is responsive to the pulse circuit signal to provide the reset signal. A control signal may vary the width of a pulse generated by the circuit by varying the length of a delay associated with the reset loop path. Both a coarse control signal, such as a signal that selectively removes a logic element in the reset loop path, and a fine control signal, such as a signal that controls a tunable delay element in the reset loop path, may be used to adjust the pulse width.

Variable width pulse generator

A pulse generating circuit includes a first pulse generating circuit for generating a first output pulse, and a second pulse generating circuit for outputting a second output pulse. Each pulse generating circuit comprises a stack of two n-channel transistors and a reset circuit. The reset circuit includes two p-channel transistors and two inverters and is provided for automatically resetting the pulse generating circuits. The second pulse generating circuit includes a delay element for introducing an additional gate delay in the generation of the second output pulse. The additional gate delay introduces an asymmetry in the output pulses which offsets or cancels a previously introduced asymmetry of an input clock signal to generate an output clock signal having a constant period. Clock gating circuitry is provided for selectively enabling and disabling at least one of said pulse generator circuits.

High gain pulse generator circuit with clock gating

A logic structure adapted to receive pulsed active input signals produces a logical output with a very small inherent switching delay. Pull-down transistors and complementary pull-up transistors are ratioed such that the default logical output level remains close to nominal even when the logic structure sinks or sources a DC current. When the pulsed input signals are inactive, no DC current path is enabled.

High speed ratioed CMOS logic structures for a pulsed input environment

A high performance register that can be used as a pipelined register in logic chips that are designed using a pulsed logic methodology is described. The register features minimal setup time, pulse catching and pulse launching. The register circuitry complies with and implements a circuit-level test methodology for pulsed logic that features the ability to inhibit the reset of pulses, to force resets and to operate the circuits in a pseudo static mode. The register also complies with the level sensitive scan design (LSSD) methodology. Also described is a state-holding static master-slave register that complies with a pulsed logic design methodology, the register exhibiting an automatic power reduction feature and a simplified modular register bit design which can easily be adapted to either static domino or pulsed logic. The register is also LSSD compliant. Also described is the means and method for allowing static transmission gate input registers to comply with the static evaluate test mode. The automatic power reduction feature can be extended to downstream logic.

High performance registers for pulsed logic

An automatic and adaptive threshold setting circuit for an IR receiver is capable of operating over a broad range of frequencies and power levels. The adaptive threshold circuit allows a very sensitive threshold in environments where little sunlight or other ambient light reaches the receiver, but which will increase the threshold of the receiver when large amounts of ambient light fall on the photo diode. The circuit senses the current flowing through the reverse biased IR photo detector due to ambient light levels. This current measurement is used to adjust the sensitivity of the receiver.

Automatic threshold setting circuit

A lateral injection group III-V heterostructure device having self-aligned graded contact diffusion regions of opposite conductivity types and a method of fabricating such devices are disclosed. The device includes a heterojunction formed by a higher bandgap III-V compound semiconductor formed over a lower bandgap III-V compound semiconductor. The method of the present invention allows the opposite conductivity type diffusion regions to diffuse simultaneously and penetrate the heterojunction. This results in compositional mixing of the compound semiconductor materials forming the heterojunction in the diffusion regions.

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Portland, OR, United States of America

Mark S Milshtein