Motorola Corporation

Emerson Network Power - Embedded Computing, Inc.

Bct Spectrum Inc.

Mark S Lanus

Charles Christopher Hill

Bruce A Hanahan

Anil Gupta

Robert Charles Tufford

Douglas L Sandy

Brent M McKay

John H Kelly

Mark Huth

Wolfgang Poschenrieder

Edward Greenwood

Bruce Rosenkrantz

James Langdal

Edward P Sayre

A chassis () for housing at least one cardcage () is disclosed. The chassis includes a first portion () of a chassis housing () through a sixth portion () thereof. The first through sixth portions forming a boundary around a storage region of the chassis housing (). The chassis () also includes at least one air moving device (). At least first () and second openings () are situated within the chassis housing (). The first and () second openings () located at substantially different elevations relative to each other. A cardcage () is located in the storage region and situated in a skewed orientation relative to at least two of the portions of the chassis housing (). The at least first () and second () openings and the at least one air moving device () are located relative to the skewed oriented cardcage () to facilitate airflow thereacross.

Skewed cardcage orientation for increasing cooling in a chassis

A power distribution system and method may include a first power domain having a first plurality of power rails, a second power domain having a second plurality of power rails, where the first power domain is electrically independent of the second power domain, and a plurality of modules coupled to the first power domain and the second power domain, where each of the plurality of modules is coupled to one of the first plurality of power rails and one of the second plurality of power rails. The system may also include a plurality of mated pairs, where each of the plurality of modules is in only one of the plurality of mated pairs, and where each of the plurality of mated pairs is coupled to two separate of the first and second plurality of power rails.

Power distribution system

A method of latent fault checking a cooling module of an embedded computer chassis may include prior to detection of an active fault in the cooling module, performing a fan controller latent fault checking algorithm and a full-speed latent fault checking algorithm. The fan controller latent fault checking algorithm may include attempting to modify a fan speed in the cooling module via a fan controller module in the cooling module, and determining if a change in the fan speed is detected. The full-speed latent fault checking algorithm may include attempting to modify the fan speed via a full speed fan control circuit, bypassing the fan controller module, and determining if the change in the fan speed is detected. If the change in the fan speed is not detected in at least one of the fan controller latent fault checking algorithm and the full-speed latent fault checking algorithm, a latent fault in the cooling module of the embedded computer chassis may be indicated.

Method of latent fault checking a cooling module

A bladed architecture, backplane-based network () having N payload slots () includes an N/2 slot switch module (), wherein the N/2 slot switch module is reconfigurable to one of a left-hand slot switch configuration () and a right-hand slot switch configuration (), and wherein the N/2 slot switch module is coupled to N/2 of the N payload slots such that the bladed architecture, backplane-based network is in a sub-optimal configuration ().

N/2 slot switch module

A power distribution system and method may include a first power domain having a first plurality of power rails, a second power domain having a second plurality of power rails, where the first power domain is electrically independent of the second power domain, and a plurality of modules coupled to the first power domain and the second power domain, where each of the plurality of modules is coupled to a unique set of one of the first plurality of power rails and one of the second plurality of power rails. The system may also include a plurality of mated pairs, where each of the plurality of modules is in only one of the plurality of mated pairs, where each of the plurality of mated pairs is coupled to four separate of the first and second plurality of power rails, and where each of the plurality of mated pairs is coupled to a unique set of the first plurality of power rails and the second plurality of power rails.

Highly available power distribution system

A method of managing memory includes providing a memory ( ) partitioned into a memory tree having N memory levels and different numbers of memory nodes ( ) at each of the memory levels, providing a memory request, determining a memory request size, recursively searching partially-full subtrees within the memory tree to identify an empty one of the memory nodes minimizing fragmentation within the memory tree, and allocating the memory request to the empty one of the memory nodes.

Method of managing memory for a PCI bus

In a method for switching between multiple system hosts (,) on a CompactPCI bus (,), a hot swap controller (,) provides to a special arbiter (,) a high priority request signal and the special arbiter (,) provides to the hot swap controller a grant signal only when the CompactPCI bus is idle. The hot swap controller (,) provides to the special arbiter (,) a float signal causing the special arbiter (,) to disable the system host signals, which include one or more grant signals for granting bus access to devices on the CompactPCI bus (,), one or more reset signals for resetting the devices, one or more interrupts and one or more clock signals provided to devices. The hot swap controller (,) transfers control of the CompactPCI bus (,) to a standby system host,).

Method for switching between multiple system hosts

In a method for swapping a system host board (150,160,170,180), when a failure is detected on a first system processor board (150), control of a first CompactPCI bus (110) is transferred from a first system processor board system host (154) to a first bridge board system host(164). In an active/standby configuration, control of a second CompactPCI bus (120) is transferred from a second bridge board system host (184) to a second system processor board system host (174), and control of the devices on the first CompactPCI bus (110) and second CompactPCI bus (120) is transferred from the first system processor (152) to the second system processor (172) without resetting any devices on the system.

Method and system for controlling a bus with multiple system hosts

In a method for switching between multiple system processors (152,172) on a CompactPCI bus (110,120), when a standby system processor (172,152) determines a failure affecting an active system processor (152,172) on the CompactPCI bus (110,120), the standby system processor (172,152) places a special arbiter (820) in a one master mode. If the standby system processor (172,152) determines that a device is at risk of performing a destructive action, the standby system processor (172,152) quiesces the device. The standby system processor (172,152) then places the special arbiter (820) in a multiple master mode.

Method for switching between multiple system processors

A multiconfiguration backplane (100) can be configured in four different configurations: dual, extended, active/standby and active/active. The multiconfiguration backplane (100) has a first COMPACT PCI bus (110) with a first system processor slot (112), a first bridge slot (114), and a first set of one or more input/output slots (116). The multiconfiguration backplane has a second COMPACT PCI bus (120) with a second system processor slot (122), a second bridge slot (124), and a second set of one or more input/output slots (126). A first cross connection (130) is between the first system processor slot (112) and the second bridge slot (124), and a second cross connection (140) is provided between the second system processor slot (122) and the first bridge slot (114). Preferably, the first cross connection is a first local PCI bus and the second cross connection is a second local PCI bus.

Multiconfiguration backplane

A process control system is disclosed in which process variables are treated as mapped in n-dimensional space, where n is the number of orthogonal directions. Three functions, set, check, and term, provide the link between expected and actual conditions. The check and term functions operate on orthogonal coordinates. Each parameter has a guard band to provide a soft boundary for the parameter.

Growing community of inventors

Tempe, AZ, United States of America

Mark S Lanus