3com Corporation

Mark S Isfeld

Bruce W Mitchell

Michael J Seaman

Tracy D Mallory

Nagaraj Arunkumar

John H Hughes

Niles E Strohl

Pyda Srisuresh

Michael H Bowman

An internetwork device manages the flow of packets of I/O data among a plurality of network interface devices. The internetwork device includes an I/O bus which is coupled to the plurality of network interface devices and a shared memory, for storing packets of I/O data and control structures needed by the plurality internetwork interface devices. The shared memory is also coupled to a processor bus, which connects to a processor and a processor memory. The processor memory is isolated from the shared memory, and is used for storing routines and internetworking information involved in routing packets of I/O data among the plurality of network interface devices. In this way, accesses between the processor and the processor memory are decoupled from accesses between the plurality of network interface devices. System performance is improved by storing copies of items from the shared memory in a processor cache located near the processor. Consistency rules are enforced between items in the shared memory and copies of the items in the processor cache through communications across the processor bus. Communications across the processor bus to enforce consistency rules are minimized by maintaining a shadow tag store near the shared memory, which keeps track of the items from the shared memory which are copied in the processor cache. Communications to enforce consistency rules only take place if the shadow tag store indicates that the processor cache contains an item of data from the shared memory which has been read from or written to.

High performance shared memory for a bridge router supporting cache

A communication technique for high volume connectionless-protocol, backbone communication links in distributed processing systems provides for control of latency and reliability of messages transmitted. The system provides for transmit list and receive list processes in the processors on the link. On the transmit side, a high priority command list and a normal priority command list are provided. In the message passing process, the command transmit function transmits commands across the backplane according to a queue priority rule that allows for control of transmit latency. Messages that require low latency are written into the high priority transmit list, while a majority of messages are written into the high throughput or normal priority transmit list. A receive filtering process in the receiving processor includes dispatch logic which dispatches messages either to a high priority receive list or a normal priority receive list. The filtering function also acts to drop messages received according to the amount of available buffer space in the receiving processor, as measured against watermarks based on reliability tags in message headers. The messages received are routed to either the high priority receive list or a normal priority receive list based on another control bit in the message headers. The receiving processor processes the messages in the receive queues according to a priority rule that allows for control of the latency between receipt of a message, and actual processing of the message by the receiving processor.

High throughput message passing process using latency and reliability

A high performance scalable networking bridge/router system is based on a backbone communication medium and message passing process which interconnects a plurality of input/output modules. The input/output modules vary in complexity from a simple network interface device having no switching or routing resources on board, to a fully functional bridge/router system. Also, in between these two extremes input/output modules which support distributed protocol processing are supported. A central internetworking engine includes a shared memory resource coupled to the backbone. The architecture includes a physical layer communication system for transferring control messages and data packets across the backbone, a logical layer interprocessor messaging system which operates over the physical layer across the backbone for communication between intelligent input/out modules, and between such modules in the central internetworking engine, and distributed protocol modules which are supported on intelligent input/output modules, and communicate using the logical interprocessor messaging system with the central internetworking resources.

Bridge/router architecture for high performance scalable networking

A digital circuit for generating a signal with a pulse width that is other than a half multiple of the clock is shown. The signal width can be greater or less than the clock period. This digital circuit includes a signal modifier, responsive to the clock signal, for generating a signal with a logic 0 state in response to the first clock edge and a signal with a logic 1 state in response to a toggle signal. A delay circuit generates the toggle signal in response to the second clock edge and a time delay measured from the second clock edge. With the appropriate delay element in the delay circuit, the generating of the toggle signal can be selectively delayed to extend the duration of the pulse.

System for generating a variable signal in response to a toggle signal

A tri-state synchronous bus driver avoids contention between succeeding cycles by shutting off each device's output enable early, so that it is guaranteed to no longer drive the line by the time any other device begins to drive. Enable activation occurs on a leading edge of the bus clock, and deactivation occurs at a delayed half phase clock edge. A low current bus holding cell is coupled to each bi-directional line to maintain the driven signal value until it can be sampled by a receiving device. This has the advantages that set up time is not eroded by the technique, and that the disable timing is relatively non-critical. The technique is particularly useful in gate array technology as process, temperature, and voltage variation can cause considerable fluctuation in the actual timing of circuits.

Driver for tri-state bus

A system uses a message passing paradigm for transferring large amounts of input/output data among a plurality of processors, such as a network intermediate system or router. A bus interconnects the plurality of processors with a plurality of bus interface devices. The bus interface device which originates a transfer includes a command list storing lists of commands which characterize transfers of data messages from local memory across the bus and a packing buffer which buffers the data subject of the command being executed between local memory and the bus. A bus interface device which receives a transfer includes a free buffer list storing pointers to free buffers in local memory into which the data may be loaded from the bus, and a receive list storing pointers to buffers in local memory loaded with data from the bus. The command list includes a first high priority command list and a second lower priority command list for managing latency of the higher priority commands in the software of the processor. The bus interface which receives the transfer includes control logic which manages data transfer into and out of an inbound buffer, including receiving burst transfers of message transfer cells from the bus, loading free buffers in local memory from the inbound buffer with message transtar cells, and updating the receive list. The receive list includes a first higher priority receive list and a second lower priority receive list for reliability management, and logic which monitors the free list so that lower priority messages may be dropped to prevent overflow of free buffer resources.

Network intermediate system with message passing architecture

An internetwork device which manages the flow of packets of I/O data among a plurality of network interface devices includes a bus coupled to the plurality of network interface devices, a core memory storing only packets of I/O data and control structures needed by the plurality of network interface devices, and a processor including local memory isolated from the core memory storing routines and internetwork information involved in updating control structures and control fields in the packets of I/O data to direct movements of packets of I/O data among the plurality of network interface devices. A bus-memory interface is provided through which transfers of packets of I/O/data and control structures used by the plurality of network interface devices are conducted between the core memory and the bus. A processor-memory interface is provided through which transfers of data to or from control structures or control fields in packets of I/O data are conducted between the core memory and the processor. Finally, a processor-bus interface is included through which configuration information concerning control structures and I/O data buffers in the core memory are transferred between the plurality of network interface devices and the processor across the bus. The processor-bus and processor-memory interfaces include structures for decoupling processor accesses to configuration stores in the plurality network interface devices and to the core memory from contention with bus-memory interface transfers between the core memory and the plurality of network interface devices.

System for managing data flow among devices by storing data and

A mixed poll-interrupt system optimizes performance of a processor managing status information indicating the occurrence of service-requiring events generated by I/O devices. Separation logic separates the status information into a first class of more time-critical status indications and a second class of less time-critical status indications. A processor interface is connected to the separation logic and the processor, and stores data identifying status indications in the first class and data identifying status indications in the second class. The processor services the events corresponding to the status indications in the first class with a relatively higher priority routine, such as an interrupt service routine, and services the events corresponding to the status indications in the second class with a relatively lower priority routine, such as a polling routine. The separation logic also includes match logic, which matches addresses or other control information generated by the I/O device, with a prespecified match value which indicates an event having a time-critical need for service. Upon detection of a match, an indication in the first class is generated and serviced by the managing processor with an interrupt service routine.

System for classifying input/output events for processes servicing the

A high performance bus suitable for high speed internetworking applications which is based on three bus phase types, including an arbitration phase, an address phase, and a data phase. The arbitration, address, and data phases share a single set of lines. Distributed arbitration logic on each of the interface devices supplies local arbitration codes to a particular line in the set of lines in the arbitration cycle, and detects an arbitration win during the same phase in response to the local arbitration code, and other arbitration codes driven on the set of lines during the arbitration cycle. Each module coupled to the bus also assigned a local priority code. During the arbitration cycle, both the arbitration code and the priority code are driven on respective subsets of the shared sets of lines. Assertion of the local priority code overrides normal requests for the bus. The arbitration logic on each module includes a bus request logic which has the effect of defining arbitration cycles, such that in a particular arbitration phase, a group of modules that asserts a bus request signal controls the bus request signal until all modules in the group have won arbitration.

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San Jose, CA, United States of America

Mark S Isfeld